參數(shù)資料
型號(hào)： ADSP-21mod970
廠商： Analog Devices, Inc.
英文描述： Multi-Port Internet Gateway Processor(多口網(wǎng)關(guān)處理器)
中文描述： 多端口Internet網(wǎng)關(guān)處理器（多口網(wǎng)關(guān)處理器）
文件頁(yè)數(shù)： 17/50頁(yè)
文件大?。?/td> 980K
代理商： ADSP-21MOD970
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ADSP-21mod970 Preliminary Data Sheet
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respectively) signals the ADSP-21mod970 that a particular transaction is required. In either case, there
is a one-processor-cycle delay for synchronization. The memory access consumes one additional
processor cycle.
Technca
3
Host uses IS and IAL control lines to latch either the DMA starting address (ID-
MAA) or the PM/DM OVLAY selection into the processor’s IDMA control registers.
If bit 15 = 1, the value of bits 7:0 represent the IDMA overlay: bits 14:8 must be set to 0.
If bit 15 = 0, the value of bits 13:0 represent the starting address of internal memory to be
accessed and bit 14 reflects PM or DM for access.
Host uses IS and IRD (or IWR) to read (or write) processor internal memory (PM or
DM).
Host checks IACK line to see if the processor has completed the previous IDMA op-
eration.
Host ends IDMA transfer.
4
5
6
The IDMA port has a 16-bit multiplexed address and data bus and supports 24-bit program memory. The
IDMA port is completely asynchronous and can be written to while the ADSP-21mod970 is operating
at full speed.
The processor memory address is latched and then automatically incremented after each IDMA
transaction. An external device can therefore access a block of sequentially addressed memory by
specifying only the starting address of the block. This increases throughput as the address does not have
to be sent for each memory access.
IDMA Port access occurs in two phases. The first is the IDMA Address Latch cycle. When the
acknowledge is asserted, a 14-bit address and 1-bit destination type can be driven onto the bus by an
external device. The address specifies an on-chip memory location, the destination type specifies
whether it is a DM or PM access. The falling edge of the address latch signal latches this value into the
IDMAA register.
Once the address is stored, data can then be either read from, or written to, the ADSP-21mod970’s on-
chip memory. Asserting the select line (IS) and the appropriate read or write line (IRD and IWR
Once an access has occurred, the latched address is automatically incremented, and another access can
occur.
Through the IDMAA register, the processor can also specify the starting address and data format for
DMA operation. Asserting the IDMA port select (IS) and address latch enable (IAL) directs the ADSP-
21mod970 to write the address onto the IAD0-14 bus into the IDMA Control Register. If bit 15 is set to
0, IDMA latches the address. If bit 15 is set to 1, IDMA latches OVLAY memory.This register, shown
in Figure 8, is memory mapped at address DM (0x3FE0). Note that the latched address (IDMAA) cannot
be read back by the host.
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