參數(shù)資料
型號： ADSP-21mod970
廠商： Analog Devices, Inc.
英文描述： Multi-Port Internet Gateway Processor(多口網(wǎng)關(guān)處理器)
中文描述： 多端口Internet網(wǎng)關(guān)處理器（多口網(wǎng)關(guān)處理器）
文件頁數(shù)： 21/50頁
文件大?。?/td> 980K
代理商： ADSP-21MOD970
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ADSP-21mod970 Preliminary Data Sheet
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Preimnary
active BR input in the following processor cycle by:
Three-stating the data and address buses and the PMS, DMS, BMS, CMS, IOMS, RD, WR
output drivers,
Asserting the bus grant (BG) signal, and
Halting program execution.
If Go Mode is enabled, the modem processor will not halt program execution until it encounters an
instruction that requires an external memory access.
Technca
A 1 in the enable bit causes the assertion of the CMS signal at the same time as the selected memory
select signal. All enable bits default to 1 at reset, except the BMS bit.
Boot Memory Select (BMS) Disable
The ADSP-21mod 970 also lets you boot the processor from one external memory space while using a
different external memory space for BDMA transfers during normal operation. You can use the CMS to
select the first external memory space for BDMA transfers and BMS to select the second external emory
space for booting. The BMS signal can be disabled by setting Bit 3 of the System Control Register to 1.
The System Control Register is illustrated in Figure 9.
Figure 9 System Control Register
Bus Request & Bus Grant
Each modem processor in the ADSP-21mod970 can relinquish control of the data and address buses to
an external device. When the external device requires access to memory, it asserts the bus request (BR)
signal. If the modem processor is not performing an external memory access, then it responds to the
If a modem processor is performing an external memory access when an external device asserts the BR
signal, then it will not three-state the memory interfaces or assert the BG signal until the processor cycle
after the access completes. The instruction does not need to be completed when the bus is granted. If a
single instruction requires two external memory accesses, the bus will be granted between the two
accesses.
When the BR signal is released, the processor releases the BG signal, re-enables the output drivers and
continues program execution from the point where it stopped.
The bus request feature operates at all times, including when the processor is booting and when RESET
is active.
The BGH pin is asserted when a modem processor is ready to execute an instruction but is stopped
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
SYSTEM CONTROL REGISTER
DM(0x3FFF)
PWAIT
PROGRAM MEMORY
WAIT STATES
BMS ENABLE
0 = ENABLED, 1 = DISABLED
SPORT0 ENABLE
1 = ENABLED, 0 = DISABLED
SPORT1 ENABLE
1 = ENABLED, 0 = DISABLED
SPORT1 CONFIGURE
1 = SERIAL PORT
0 = FI, FO, IRQ0, IRQ1, SCLK
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-21MOD970-000 制造商:Analog Devices 功能描述:
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ADSP21MOD980N 制造商:AD 制造商全稱:Analog Devices 功能描述:MultiPort Internet Gateway Processor
ADSP-21MSP50ABG-52 制造商:Analog Devices 功能描述:
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