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ADSP-21mod970 Preliminary Data Sheet
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Technca
characteristics.
Note:
If your target does not meet the worst case chip specification for memory access parameters, you
may not be able to emulate your circuitry at the desired CLKIN frequency. Depending on the severity of
the specification violation, you may have trouble manufacturing your system as processor components
statistically vary in switching characteristic and timing requirements within published limits.
Restriction:
All memory strobe signals on the ADSP-21mod970 (RD, WR, PMS, DMS, BMS, CMS,
and IOMS) used in your target system must have 10 kW pull-up resistors connected when the EZ-ICE
is being used. The pull-up resistors are necessary because there are no internal pull-ups to guarantee their
state during prolonged three-state conditions resulting from typical EZ-ICE debugging sessions. These
resistors may be removed at your option when the EZ-ICE is not being used.
Target System Interface Signals
When the EZ-ICE board is installed, the performance on some system signals change. Design your sys-
tem to be compatible with the following system interface signal changes introduced by the EZ-ICE
board:
EZ-ICE emulation introduces an 8 ns propagation delay between your target circuitry and
the processor on the RESET signal.
EZ-ICE emulation introduces an 8 ns propagation delay between your target circuitry and
the processor on the BR signal.
EZ-ICE emulation ignores RESET and BR when single- stepping.
EZ-ICE emulation ignores RESET and BR when in Emulator Space (processor halted).
EZ-ICE emulation ignores the state of target BR in certain modes. As a result, the target
system may take control of the processor’s external memory bus only if bus grant (BG) is
asserted by the EZ-ICE board’s processor.