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參數(shù)資料
| 型號： | ADSP-21mod970 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multi-Port Internet Gateway Processor(多口網(wǎng)關(guān)處理器) |
| 中文描述： | 多端口Internet網(wǎng)關(guān)處理器（多口網(wǎng)關(guān)處理器） |
| 文件頁數(shù)： | 11/50頁 |
| 文件大?。?/td> | 980K |
| 代理商： | ADSP-21MOD970 |
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ADSP-21mod970 Preliminary Data Sheet
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Preimnary
time the modem pool takes to come out of the idle state (a maximum of
n
cycles).
Technca
Idle
When the ADSP-21mod970 is in the Idle Mode, the modem pool waits indefinitely in a low power state
until an interrupt occurs. When an unmasked interrupt occurs, it is serviced; execution then continues
with the instruction following the IDLE instruction. In Idle mode IDMA, BDMA and autobuffer cycle
steals still occur.
Slow Idle
The IDLE instruction is enhanced on the ADSP-21mod970 to let the modem pool’s internal clock signal
be slowed, further reducing power consumption. The reduced clock frequency, a programmable fraction
of the normal clock rate, is specified by a selectable divisor given in the IDLE instruction.
The format of the instruction is
IDLE (n);
where n = 16, 32, 64, or 128. This instruction keeps the modem pool fully functional, but operating at
the slower clock rate. While it is in this state, the modem pool’s other internal clock signals, such as
SCLK, CLKOUT, and timer clock, are reduced by the same ratio. The default form of the instruction,
when no clock divisor is given, is the standard IDLE instruction.
When the IDLE (
n
) instruction is used, it effectively slows down the modem pool’s internal clock and
thus its response time to incoming interrupts. The one-cycle response time of the standard idle state is
increased by n, the clock divisor. When an enabled interrupt is received, the ADSP-21mod970 will
remain in the idle state for up to a maximum of
n
modem pool cycles (
n
= 16, 32, 64, or 128) before
resuming normal operation.
When the IDLE (
n
) instruction is used in systems that have an externally generated serial clock (SCLK),
the serial clock rate may be faster than the modem pool’s reduced internal clock rate. Under these
conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional
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| ADSP-21MOD970-000 | 制造商:Analog Devices 功能描述: |
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