參數(shù)資料
型號(hào)： ADSP-21mod970
廠商： Analog Devices, Inc.
英文描述： Multi-Port Internet Gateway Processor(多口網(wǎng)關(guān)處理器)
中文描述： 多端口Internet網(wǎng)關(guān)處理器（多口網(wǎng)關(guān)處理器）
文件頁數(shù)： 31/50頁
文件大小： 980K
代理商： ADSP-21MOD970
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ADSP-21mod970 Preliminary Data Sheet
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Preimnary
Data
Technca
Capacitive Loading
Figures 13 and 14 show the capacitive loading characteristics of the ADSP-21mod970.
Figure 13 Typical Output Rise Time vs. Load Capacitance,
CL (at Maximum Ambient Operating Temperature)
Figure 14 Typical Output Valid Delay or Hold vs. Load Capacitance, C
L
(at Maximum Ambient Operating Temperature)
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they have stopped driving and started a transition from
the measured output high or low voltage to a high impedance state. The output disable time (t
DIS
) is the
difference of t
MEASURED
and t
DECAY
, as shown in the Output Enable/Disable diagram. The time is the
interval from when a reference signal reaches a high or low voltage level to when the output voltages
have changed by 0.5 V from the measured output high or low voltage.
The decay time, t
DECAY
, is dependent on the capacitive load, CL, and the current load, iL, on the output
TBD
TBD
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