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參數(shù)資料
| 型號： | ADSP-21mod970 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multi-Port Internet Gateway Processor(多口網(wǎng)關(guān)處理器) |
| 中文描述： | 多端口Internet網(wǎng)關(guān)處理器（多口網(wǎng)關(guān)處理器） |
| 文件頁數(shù)： | 4/50頁 |
| 文件大?。?/td> | 980K |
| 代理商： | ADSP-21MOD970 |
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ADSP-21mod970 Preliminary Data Sheet
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Figure 1 ADSP-21mod970 Modem Pool
Each individual modem processor has a DSP core, 160K bytes of RAM, two serial ports, and a DMA
port. The signals for a single processor are show in Figure 2. The signals of each modem processor are
accessed through the external pins of the ADSP-21mod970. Some signals are bussed with the signals of
the other processors and are accessed through a single external pin. Other signals remain separate and
they are accessed through separate external pins for each processor.
Technca
ARCHITECTURE OVERVIEW
Figure 1 is an overall block diagram of the ADSP-21mod970 modem pool. The modem pool contains
six independent digital modem processors.
Modem
Channel
Modem
Channel
Modem
Channel
4
Modem
Channel
5
Modem
Channel
6
Modem
Channel
1
DATA <23:8>
CLKIN
IAD <15:0>
IDMA Cntl
DATA <23:8>
CLKIN, Bus Cntl
IAD <15:0>
IDMA Cntl
SPORT 0a
SPORT 1
Emulator
SPORT 0b
16
4
16
16
9
16
4
4
4
8
4
IDMA Cntl = IAL, IRD, IWR, IACK
Flags = FL<0:2>, PF<0:7>
Bus Cntl = A0, BMS, PMS, DMA, CMS, IOMS, RD, WR
Emulator = EMS, EINT, ELIN, EBR, EBG, ECLK, ELOUT, ERESET
SPORT 0a, SPORT 0b = RFS0, DR0, DT0. SCLK0
SPORT 1 = RFS1, DR1, SCLK1
The following signals are routed to each
ADSP-21mod970:
BR<5:0>
BG<5:0>
BGH<5:0>
Flags
RESET<5:0>
CLKOUT<5:0>
EE<5:0>
IS<5:0>
TFS0<5:0>
DT1<5:0>
6
6
6
66
6
6
6
6
6
6
Notes:
1) PWD is tied HIGH in PBGA
2) Vdd and Gnd use power and ground
planes in PBGA
3) IRQ functions are multiplexed on die with
programmable flags (See ADSP-21mod970
data sheet)
Gnd
Vdd
55
27
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21MOD970-000 | 制造商:Analog Devices 功能描述: |
| ADSP-21MOD980-000 | 制造商:Analog Devices 功能描述: |
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