參數(shù)資料
型號(hào)： ADSP-21mod970
廠商： Analog Devices, Inc.
英文描述： Multi-Port Internet Gateway Processor(多口網(wǎng)關(guān)處理器)
中文描述： 多端口Internet網(wǎng)關(guān)處理器（多口網(wǎng)關(guān)處理器）
文件頁(yè)數(shù)： 13/50頁(yè)
文件大?。?/td> 980K
代理商： ADSP-21MOD970
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ADSP-21mod970 Preliminary Data Sheet
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Preimnary
Figure 6 shows Program Memory, while Figure 7 shows Data Memory. Table 2 summarizes ADSP-
21mod970 operating modes. Table 3 explains the mode bits and memory booting.
Technca
any time after power up, the clocks continue to run and do not require stabilization time.
The power-up sequence is defined as the total time required for the oscillator circuits to stabilize after a
valid V
DD
is applied to the processors, and for the internal phase-locked loops (PLL) to lock onto the
specific frequency. A minimum of 2000 CLKIN cycles ensures that the PLLs have locked, but this does
not include the oscillators start-up time. During this power-up sequence, the RESET signals should be
held low. On any subsequent resets, the RESET signals must meet the minimum pulse width
specification, t
RSP
.
The RESET inputs contains some hysteresis; however, if you use an RC circuit to generate your RESET
signals, the use of an external Schmidt triggers are recommended.
The reset for each individual modem processor sets the internal stack pointers to the empty stack
condition, masks all interrupts and clears the MSTAT register. When a RESET is released, if there is no
pending bus request and the modem processor is configured for booting, the boot-loading sequence is
performed. The first instruction is fetched from on-chip program memory location 0x0000 once boot
loading completes.
MEMORY ARCHITECTURE
The ADSP-21mod970 provides a variety of memory and peripheral interface options for Modem
Processor 1. The key functional groups are Program Memory, Data Memory, Byte Memory, and I/O.
Refer to the following figures and tables for PM and DM memory allocations in the ADSP-21mod970.
The ADSP-21mod970 modem pool operates in one of two memory modes: Slave Mode or Master Mode.
The memory modes determine the memory access to Modem Processor 1. In Slave Mode, the memory
of Modem Processor 1 is configured for Host mode; in Master Mode, the memory of Modem Processor
1 is configured for Full-Memory mode. Memories for Modem Processors 2–6 are configured only for
Host Mode. The differences between these memory modes are explained in the following sections.
Table 2 Processor and Memory Modes
Memory Modes
for
Modem Processor1
ADSP-21mod970 Modes
Master
Slave
Host
NA
All internal program memory available
All internal data memory available
IDMA port enabled
Full- Memory
All internal and external program memory available
All internal and external data memory available
I/O space available
Byte memory DMA (BDMA) enabled
NA
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