參數(shù)資料
型號(hào)： ADSP-21mod970
廠商： Analog Devices, Inc.
英文描述： Multi-Port Internet Gateway Processor(多口網(wǎng)關(guān)處理器)
中文描述： 多端口Internet網(wǎng)關(guān)處理器（多口網(wǎng)關(guān)處理器）
文件頁(yè)數(shù)： 24/50頁(yè)
文件大?。?/td> 980K
代理商： ADSP-21MOD970
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ADSP-21mod970 Preliminary Data Sheet
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Data
Figure 11 Target Board Connector for EZ-ICE
The 14-pin, 2-row pin strip header is keyed at the Pin 7 location—you must remove Pin 7 from the
header. The pins must be 0.025 inch square and at least 0.20 inch in length. Pin spacing should be 0.1 x
0.1 inches. The pin strip header must have at least 0.15 inch clearance on all sides to accept the EZ-ICE
probe plug.
Technca
RESET
The following pins are also used by the EZ-ICE:
BR
BG
RESET
GND
The EZ-ICE uses the EE (emulator enable) signal to take control of the ADSP-21mod970 in the target
system. This causes the processor to use its ERESET, EBR, and EBG pins instead of the RESET, BR,
and BG pins. The BG output is three-stated. These signals do not need to be jumper-isolated in your
system.
The EZ-ICE connects to your target system via a ribbon cable and a 14-pin female plug. The female plug
is plugged onto the 14-pin connector (a pin strip header) on the target board.
Target Board Connector for EZ-ICE Probe
The EZ-ICE connector (a standard pin strip header) is shown in Figure 11. You must add this connector
to your target board design if you intend to use the EZ-ICE. Be sure to allow enough room in your system
to fit the EZ-ICE probe onto the 14-pin connector.
Pin strip headers are available from vendors such as 3M, McKenzie, and Samtec.
Target Memory Interface
For your target system to be compatible with the EZ-ICE emulator, it must comply with the memory
interface guidelines listed below.
PM, DM, BM, IOM, & CM
Design your Program Memory (PM), Data Memory (DM), Byte Memory (BM), I/O Memory (IOM),
and Composite Memory (CM) external interfaces to comply with worst case device timing requirements
and switching characteristics as specified in this data sheet. The performance of the EZ-ICE may
approach published worst case specification for some memory access timing requirements and switching
GND
EBG
EBR
KEY (NO PIN)
ELOUT
EE
BG
BR
ELIN
ECLK
EMS
ERESET
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