參數(shù)資料
型號(hào)： ADSP-21mod970
廠商： Analog Devices, Inc.
英文描述： Multi-Port Internet Gateway Processor(多口網(wǎng)關(guān)處理器)
中文描述： 多端口Internet網(wǎng)關(guān)處理器（多口網(wǎng)關(guān)處理器）
文件頁數(shù)： 28/50頁
文件大?。?/td> 980K
代理商： ADSP-21MOD970
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ADSP-21mod970 Preliminary Data Sheet
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Preimnary
Ambient Temperature Rating:
T
AMB
= T
CASE
– (PD x
θ
CA)
T
CASE
= Case Temperature in °C
PD = Power Dissipation in W
θ
CA
= Thermal Resistance (Case-to-Ambient)
θ
JA
= Thermal Resistance (Junction-to-Ambient)
θ
JC
= Thermal Resistance (Junction-to-Case)
Technca
MEMORY TIMING SPECIFICATIONS
The table below shows common memory device specifications and the corresponding ADSP-21mod970
timing parameters, for your convenience.
NOTE: xMS = PMS, DMS, BMS, CMS, IOMS
FREQUENCY DEPENDENCY FOR TIMING SPECIFICATIONS
t
CK
is defined as 0.5t
CKI
. The ADSP-21mod970 uses an input clock with a frequency equal to half the
instruction rate: a 26.32 MHz input clock (which is equivalent to 38.0 ns) yields a 19 ns processor cycle
(equivalent to 52 MHz). t
CK
values within the range of 0.5t
CKI
period should be substituted for all
relevant timing parameters to obtain the specification value.
Example: t
CKH
= 0.5t
CK
– 7 ns = 0.5 (19 ns) – 7 ns = 2.5 ns
ENVIRONMENTAL CONDITIONS
POWER DISSIPATION
To determine total power dissipation in a specific application, the following equation should be applied
for each output:
C x V
DD
2 x f
Table 6: Memory Devices and Timing Parameters
Memory Device
Specification
ADSP-
21mod970
Timing
Parameter
Timing
Parameter
Definition
Address setup to
Write Start
Address Setup to
Write End
Address Hold Time
Data Setup Time
Data Hold Time
OE to Data Valid
Address Access Time
t
ASW
t
t
WRA
t
DW
t
DH
t
AA
A0-A13, xMS Setup before WR
Low
A0-A13, xMS Setup before WR
A0-A13, xMS Hold before WR
Low
Data Setup before WR High
Data Hold after WR High
A0-A13, xMS to Data Valid
Package
PBGA
θ
JA
TBD
θ
JC
TBD
θ
CA
TBD
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