- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375267 > ADSP-21mod970 (Analog Devices, Inc.) Multi-Port Internet Gateway Processor(多口網(wǎng)關(guān)處理器) PDF資料下載
參數(shù)資料
| 型號： | ADSP-21mod970 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multi-Port Internet Gateway Processor(多口網(wǎng)關(guān)處理器) |
| 中文描述： | 多端口Internet網(wǎng)關(guān)處理器（多口網(wǎng)關(guān)處理器） |
| 文件頁數(shù)： | 12/50頁 |
| 文件大?。?/td> | 980K |
| 代理商： | ADSP-21MOD970 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當(dāng)前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁
2FWREHU
ADSP-21mod970 Preliminary Data Sheet
7KLVLQIRUPDWLRQDSSOLHVWR DSURGXFWXQGHUGHYHORSPHQW ,WVFKDUDFWHULVWLFVDQGVSHFLILFDWLRQVDUHVXEMHFWWRFKDQJHZLWKRXW
QRWLFH $QDORJ 'HYLFHV DVVXPHV QR REOLJDWLRQ UHJDUGLQJ IXWXUH PDQXIDFWXULQJ XQOHVV RWKHUZLVH DJUHHG WR LQ ZULWLQJ
5(93U$
Preimnary
Data
CLOCK SIGNALS
Technca
SYSTEM CONFIGURATION
Figure 5 shows a typical multichannel modem configuration with the ADSP-21mod970. A line interface
can be used to connect the multichannel subscriber or client data stream to the multichannel serial port
of the ADSP-21mod970. The ADSP-21mod970 can support up to 64 channels. The IDMA port of the
ADSP-21mod970 is used to give a host processor full access to the internal memory of the ADSP-
21mod970. This lets the host dynamically configure the ADSP-21mod970 by loading code and data into
its internal memory. This configuration also lets the host access server data directly from the ADSP-
21mod970’s internal memory. In this configuration, the Modem Processor 1 should be put into host
memory mode where mode D =1, mode C = 1, mode B = 0, and mode A = 1 (see Table 2).
Figure 5 Multichannel Modem Configuration
The ADSP-21mod970 is clocked by a TTL-compatible clock signal that runs at half the instruction rate;
a 26 MHz input clock yields a 19 ns processor cycle (which is equivalent to 52 MHz). Normally,
instructions are executed in a single processor cycle. All device timing is relative to the internal
instruction clock rate, which is indicated by the CLKOUT signal when enabled. The clock input signal
is connected to the processor’s CLKIN input.
The CLKIN input cannot be halted, changed during operation, or operated below the specified frequency
during normal operation. The only exception is while the processor is in the power down state. For
additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual
for a detailed explanation
of this power down feature.
A clock output (CLKOUT) signal is generated by the processor at the processor’s cycle rate.
Reset
The RESET signals initiate a reset of each modem processor in the ADSP-21mod970. The RESET
signals must be asserted during the power-up sequence to assure proper initialization. RESET during
initial power-up must be held long enough to let the internal clocks stabilize. If RESETs are activated
T1/E1
LINE
INTERFACE
HOST
MICRO
PATRIOT
(SLAVE MODE)
PATRIOT
(SLAVE MODE)
PATRIOT
(SLAVE MODE)
PATRIOT
(SLAVE MODE)
SPORT
SPORT
SPORT
SPORT
IDMA
PAL
HOST CONTROL
HOST ADDRESS
HOST DATA
STATUS
&
CONTROL
PAL
IDMA CONTROL
IDMA ADDRESS
STATUS
&
CONTROL
ST/CNTL
ST/CNTL
ST/CNTL
ST/CNTL
IDMA
IDMA
IDMA
IDMA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADSP-21msp58 | DSP Microcomputer(DSP 微計算機(jī)) |
| ADSP-21MSP59 | DSP Microcomputer(DSP 微計算機(jī)) |
| ADSP-BF535 | Blackfin Embedded Processor |
| ADSP-BF535PBB-200 | Blackfin Embedded Processor |
| ADSP-BF535PBB-300 | Blackfin Embedded Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21MOD970-000 | 制造商:Analog Devices 功能描述: |
| ADSP-21MOD980-000 | 制造商:Analog Devices 功能描述: |
| ADSP21MOD980N | 制造商:AD 制造商全稱:Analog Devices 功能描述:MultiPort Internet Gateway Processor |
| ADSP-21MSP50ABG-52 | 制造商:Analog Devices 功能描述: |
| adsp-21msp50akg-52 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。