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ADSP-21mod970 Preliminary Data Sheet
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Technca
because the external bus is already granted to another device. The other device can release the bus by
deasserting bus request. Once the bus is released, the modem processor deasserts BG and BGH and
executes the external memory access.
When the ADSP-21mod970 is powered up, all the modem processors must relinquish bus control, and
only one processor at a time may control the bus.
Flag I/O Pins
Each modem processor has eight general purpose programmable input/output flag pins. They are
controlled by two memory mapped registers. The PFTYPE register determines the direction, 1 = output
and 0 = input. The PFDATA register is used to read and write the values on the pins. Data being read
from a pin configured as an input is synchronized to the ADSP-21mod970’s clock. Bits that are
programmed as outputs will read the value being output. The PF pins default to input during reset.
In addition to the programmable flags, each modem processor has three fixed-mode output flags, FL0,
FL1, and FL2.
Note: Pins PF0, PF1, PF2 and PF3 are also used for device configuration during reset.
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
The ADSP-21mod970 has on-chip emulation support and an ICE-Port, a special set of pins that interface
to the EZ-ICE. These features allow in-circuit emulation without replacing the target system processor
by using only a 14-pin connection from the target system to the EZ-ICE. Target systems must have a 14-
pin connector to accept the EZ-ICE’s in-circuit probe, a 14-pin plug.
The EZ-ICE can emulate only one modem processor at a time. You must include hardware to select
which processor in the ADSP-21mod970 you want to emulate. Figure 10 is a functional representation
of the modem processor selection hardware. You can use one ICE-Port connector with two ADSP-
21mod970 processors without using additional buffers.