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參數(shù)資料
| 型號： | 28F1604C3 |
| 廠商： | Intel Corp. |
| 英文描述： | 3 Volt Advanced+ Stacked Chip Scale Package Memory(3V閃速存儲器和靜態(tài)存儲器) |
| 中文描述： | 3伏高級堆疊芯片級封裝存儲器（3V的閃速存儲器和靜態(tài)存儲器） |
| 文件頁數(shù)： | 7/64頁 |
| 文件大?。?/td> | 927K |
| 代理商： | 28F1604C3 |
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28F1602C3, 28F1604C3, 28F3204C3
Preliminary
1
1.0
Introduction
This document contains the specifications for the 3 Volt Advanced+ Stacked Chip Scale Package
(Intel
Stacked-CSP) memory. These stacked memory solutions are offered in the following
combinations: 32-Mbit flash + 4-Mbit SRAM, 16-Mbit flash + 4-Mbit SRAM, or 16-Mbit flash
memory + 2-Mbit SRAM.
1.1
Document Conventions
Throughout this document, the following conventions have been adopted.
Voltages:
“2.7 V” refers to the full voltage range, 2.7 V–3.3V; 12 V refers to 11.4 V to 12.6 V
Main block(s)
: 32-Kword block
Parameter block(s)
: 4-Kword block
1.2
Product Overview
The 3 Volt Advanced+ Stacked-CSP combines flash and SRAM into a single package.
The Intel Stacked-CSP memory provides secure low-voltage memory solutions for portable
applications. This memory family combines two memory technologies, flash memory and SRAM,
in one package. The flash memory delivers enhanced security features, a block locking capability
that allows instant locking/unlocking of any flash block with zero-latency, and a 128-bit protection
register that enable unique device identification, to meet the needs of next generation portable
applications. Improved 12 V production programming can be used to improve factory throughput.
NOTE:
1. All words are 16 bits each.
The flash device is asymmetrically-blocked to enable system integration of code and data storage
in a single device. Each flash block can be erased independently of the others up to 1,000,000
times. The flash has eight 8-KB parameter blocks located at either the top (denoted by -T suffix) or
the bottom (-B suffix) of the address map in order to accommodate different microprocessor
protocols for kernel code location. The remaining flash memory is grouped into 32-Kword main
blocks. Any individual flash block can be locked or unlocked instantly to provide complete
protection for code or data (see
Section 4.7, “Flash Erase and Program Timings(1)” on page 25
for
details).
The flash contains both a Command User interface (CUI) and a Write State Machine (WSM). The
CUI serves as the interface between the microcontroller and the internal operation of the flash
memory. The internal WSM automatically executes the algorithms and timings necessary for
Table 1. Block Organization (x16)
(1)
Memory Device
Kwords
32-Mbit Flash
2048
16-Mbit Flash
1024
2-Mbit SRAM
128
4-Mbit SRAM
256
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