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參數(shù)資料
| 型號： | 28F1604C3 |
| 廠商： | Intel Corp. |
| 英文描述： | 3 Volt Advanced+ Stacked Chip Scale Package Memory(3V閃速存儲器和靜態(tài)存儲器) |
| 中文描述： | 3伏高級堆疊芯片級封裝存儲器（3V的閃速存儲器和靜態(tài)存儲器） |
| 文件頁數(shù)： | 16/64頁 |
| 文件大?。?/td> | 927K |
| 代理商： | 28F1604C3 |
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28F1602C3, 28F1604C3, 28F3204C3
10
Preliminary
outputs status register data when read (see Appendix A,
Program Suspend/Resume Flowchart
s)
after the Program Resume command is written. F-V
PP
must remain at the same F-V
PP
level used
for program while in program suspend mode. F-RP# must also remain at V
IH
.
3.6
Block Erase (20H)
To erase a block, write the Erase Set
-
up and Erase Confirm commands to the CUI, along with an
address identifying the block to be erased. This address is latched internally when the Erase
Confirm command is issued. Block erasure results in all bits within the block being set to “1.” Only
one block can be erased at a time. The WSM will execute a sequence of internally timed events to
program all bits within the block to “0,” erase all bits within the block to “1,” then verify that all
bits within the block are sufficiently erased. While the erase executes, status bit 7 is a “0.”
When the status register indicates that erasure is complete, check the erase status bit to verify that
the erase operation was successful. If the Erase operation was unsuccessful, SR.5 of the status
register will be set to a “1,” indicating an erase failure. If F-V
PP
was not within acceptable limits
after the Erase Confirm command was issued, the WSM will not execute the erase sequence;
instead, SR.5 of the status register is set to indicate an erase error, and SR.3 is set to a “1” to
identify that F-V
PP
supply voltage was not within acceptable limits.
After an erase operation, clear the status register (50H) before attempting the next operation. Any
CUI instruction can follow after erasure is completed; however, to prevent inadvertent status
register reads, it is advisable to place the flash in read array mode after the erase is complete.
3.6.1
Suspending and Resuming Erase (B0H/D0H)
Since an erase operation requires on the order of seconds to complete, an Erase Suspend command
is provided to allow erase
-
sequence interruption in order to read data from or program data to
another block in memory. Once the erase sequence is started, writing the Erase Suspend command
to the CUI suspends the erase sequence at a predetermined point in the erase algorithm. The status
register will indicate if/when the erase operation has been suspended. Erase suspend latency is
specified by t
WHRH2
/t
EHRH2
.
A Read Array/Program command can now be written to the CUI to read/program data from/to
blocks other than that which is suspended. This nested Program command can subsequently be
suspended to read yet another location. The only valid commands while erase is suspended are
Read Status Register, Read Configuration, Read Query, Program Setup, Program Resume, Erase
Resume, Lock Block, Unlock Block and Lock-Down Block. During erase suspend mode, the chip
can be placed in a pseudo
-
standby mode by taking F-CE# to V
IH
. This reduces active current
consumption.
Erase Resume continues the erase sequence when F-CE# = V
IL
. As with the end of a standard erase
operation, the status register must be read and cleared before the next instruction is issued.
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相關(guān)代理商/技術(shù)參數(shù) |
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