參數(shù)資料
型號(hào)： 28F1604C3
廠商： Intel Corp.
英文描述： 3 Volt Advanced+ Stacked Chip Scale Package Memory(3V閃速存儲(chǔ)器和靜態(tài)存儲(chǔ)器)
中文描述： 3伏高級(jí)堆疊芯片級(jí)封裝存儲(chǔ)器（3V的閃速存儲(chǔ)器和靜態(tài)存儲(chǔ)器）
文件頁(yè)數(shù)： 42/64頁(yè)
文件大小： 927K
代理商： 28F1604C3
28F1602C3, 28F1604C3, 28F3204C3
36
Preliminary
NOTES:
1. Substrate connections refer to ballout locations shown in
Figure 1
.
2. 0.1
μ
f capacitors should be used with D9, D10, A10and E4.
3. Some SRAM devices do not have a S-V
SSQ
; in this case, this pad is a S-V
SS
.
4. Some SRAM devices do not have a S-V
SSQ
; in this case, this pad is a V
CC
6.4
Simultaneous Operation
The term simultaneous operation in used to describe the ability to read or write to the SRAM while
also programming or erasing flash. In addition, F-CE#, S-CS
1
# and S-CS
2
should not be enabled at
the same time. (See
Table 2, “3 Volt Advanced+ Stacked-CSP Ball Descriptions” on page 3
for a
summary of recommended operating modes.) Simultaneous operation of the can be summarized by
the following:
SRAM read/write are during a Flash Program or Erase Operation are allowed.
Simultaneous Bus Operations between the Flash and SRAM are
not
allowed (because of bus
contention).
6.4.1
SRAM Operation during Flash “Busy”
This functionality provides the ability to use both the flash and the SRAM “at the same time”
within a system, similar to the operation of two devices with separate footprints. This operation can
be achieved by following the appropriate timing constraints within a system.
Figure 13. Typical Flash + SRAM Substrate Power and Ground Connections
S-V
SSQ
D10
SRAM DIE
FLASH DIE
SUBSTRATE
XX
S-X
F-X
Substrate connection to package ball
SRAM die bond pad connection
Flash die bond pad connection
S-V
CCQ
S-V
CC
S-V
SS
F-V
PP
F-V
SSQ
F-V
CC
F-V
CCQ
F-V
SS
H8
A9
D9
E4
D3
A10
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