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參數(shù)資料
| 型號(hào)： | 28F1604C3 |
| 廠商： | Intel Corp. |
| 英文描述： | 3 Volt Advanced+ Stacked Chip Scale Package Memory(3V閃速存儲(chǔ)器和靜態(tài)存儲(chǔ)器) |
| 中文描述： | 3伏高級(jí)堆疊芯片級(jí)封裝存儲(chǔ)器（3V的閃速存儲(chǔ)器和靜態(tài)存儲(chǔ)器） |
| 文件頁數(shù)： | 21/64頁 |
| 文件大小： | 927K |
| 代理商： | 28F1604C3 |
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28F1602C3, 28F1604C3, 28F3204C3
Preliminary
15
NOTES:
1.
“–” indicates no change in the current state.
2. In this table, the notation [XYZ] denotes the locking state of a block, where X = WP#, Y = DQ
, and Z = DQ
0
.
The current locking state of a block is defined by the state of WP# and the two bits of the block lock status
(DQ
, DQ
). DQ
indicates if a block is locked (1) or unlocked (0). DQ
1
indicates if a block has been locked-
down (1) or not (0).
3. At power-up or device reset, all blocks default to Locked state [001] (if WP# = 0). Holding WP# = 0 is the
recommended default.
4. The “Erase/Program Allowed” column shows whether erase and program operations are enabled (Yes) or
disabled (No) in that block’s current locking state.
5. The “Lock Command Input Result [Next State]” column shows the result of writing the three locking
commands (Lock, Unlock, Lock-Down) in the current locking state. For example, “Goes To [001]” would
mean that writing the command to a block in the current locking state would change it to [001].
6. The 128-bits of the protection register are divided into two 64-bit segments. One of the segments is
programmed at the Intel factory with a unique 64-bit number, which is unchangeable. The other segment is
left blank for customer designs to program as desired. Once the customer segment is programmed, it can be
locked to prevent reprogramming.
3.8
128-Bit Protection Register
The 3 Volt Advanced+ Stacked-CSP architecture includes a 128-bit protection register than can be
used to increase the security of a system design. For example, the number contained in the
protection register can be used to “mate” the flash component with other system components such
as the CPU or ASIC, preventing device substitution.
3.8.1
Reading the Protection Register
The protection register is read in the configuration read mode. The device is switched to this mode
by writing the Read Configuration command (90H). Once in this mode, read cycles from addresses
shown in Appendix E retrieve the specified information. To return to read array mode, write the
Read Array command (FFH).
3.8.2
Programming the Protection Register (C0H)
The protection register bits are programmed using the two-cycle Protection Program command.
The 64-bit number is programmed 16 bits at a time for word-wide parts. First write the Protection
Program Setup command, C0H. The next write to the device will latch in address and data and
program the specified location. The allowable addresses are shown in Appendix E. See
Figure 20,
“Protection Register Programming Flowchart” on page 44
.
Table 8. Block Locking State Transitions
Current State
Erase/
Program
Allowed
Next State after Command Input
WP#
DQ
1
DQ
0
Name
Lock
Unlock
Lock-Down
0
0
0
Unlocked
Yes
Go To [001]
–
Go To [011]
1
0
0
Unlocked
Yes
Go To [101]
–
Go To [111]
0
0
1
Locked
(Default)
No
–
Go To [000]
Go To [011]
1
0
1
Locked
No
–
Go To [100]
Go To [111]
0
1
1
Locked-Down
No
–
–
–
1
1
0
Lock-Down
Disabled
Yes
Go To [111]
–
Go To [111]
1
1
1
No
-
Go To [110]
–
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