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參數(shù)資料
| 型號： | 28F1604C3 |
| 廠商： | Intel Corp. |
| 英文描述： | 3 Volt Advanced+ Stacked Chip Scale Package Memory(3V閃速存儲器和靜態(tài)存儲器) |
| 中文描述： | 3伏高級堆疊芯片級封裝存儲器（3V的閃速存儲器和靜態(tài)存儲器） |
| 文件頁數(shù)： | 14/64頁 |
| 文件大?。?/td> | 927K |
| 代理商： | 28F1604C3 |
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28F1602C3, 28F1604C3, 28F3204C3
8
Preliminary
The Read Configuration mode outputs three types of information: the manufacturer/device
identifier, the block locking status, and the protection register. The device is switched to this mode
by writing the Read Configuration command (90H). Once in this mode, read cycles from addresses
shown in Table 4 retrieve the specified information. To return to read array mode, write the Read
Array command (FFH).
NOTES:
1. See
Section 3.7
for valid lock status outputs.
2.
“XX” specifies the block address of lock configuration being read.
3. See
Section 3.8
for protection register information.
4. Other locations within the configuration address space are reserved by Intel for future use.
3.3
Read Status Register (70H)
The status register indicates the status of device operations, and the success/failure of that
operation. The Read Status Register (70H) command causes subsequent reads to output data from
the status register until another command is issued. To return to reading from the array, issue a
Read Array (FFH) command.
The status register bits are output on DQ
0
–DQ
7
. The upper byte, DQ
8
–DQ
15
, outputs 00H during a
Read Status Register command.
The contents of the status register are latched on the falling edge of F-OE# or F-CE#, whichever
occurs last. This prevents possible bus errors which might occur if status register contents change
while being read. F-CE# or F-OE# must be toggled with each subsequent status read, or the status
register will not indicate completion of a program or erase operation.
When the WSM is active, SR.7 will indicate the status of the WSM; the remaining bits in the status
register indicate whether the WSM was successful in performing the desired operation (see
Table 6, “Flash Memory Status Register Definition” on page 12
).
3.3.1
Clear Status Register (50H)
The WSM sets status bits 1 through 7 to “1,” and clears bits 2, 6 and 7 to “0,” but cannot clear
status bits 1 or 3 through 5 to “0.” Because bits 1, 3, 4 and 5 indicate various error conditions, these
bits can only be cleared through the use of the Clear Status Register (50H) command. By allowing
the system software to control the resetting of these bits, several operations may be performed
(such as cumulatively programming several addresses or erasing multiple blocks in sequence)
before reading the status register to determine if an error occurred during that series. Clear the
Table 4. Read Configuration Table
Item
Address
Data
Manufacturer Code (x16)
00000
0089
Device ID (See Appendix D)
00001
ID
Block Lock Configuration
(1)
Block Is Unlocked
Block Is Locked
Block Is Locked-Down
Protection Register Lock
3
XX002
(2)
LOCK
DQ
0
= 0
DQ
0
= 1
DQ
1
= 1
80
PR-LK
Protection Register (x16)
81-88
PR
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