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參數(shù)資料
| 型號： | 28F1604C3 |
| 廠商： | Intel Corp. |
| 英文描述： | 3 Volt Advanced+ Stacked Chip Scale Package Memory(3V閃速存儲器和靜態(tài)存儲器) |
| 中文描述： | 3伏高級堆疊芯片級封裝存儲器（3V的閃速存儲器和靜態(tài)存儲器） |
| 文件頁數(shù)： | 18/64頁 |
| 文件大?。?/td> | 927K |
| 代理商： | 28F1604C3 |
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28F1602C3, 28F1604C3, 28F3204C3
12
Preliminary
NOTE:
A Command Sequence Error is indicated when SR.4, SR.5 and SR.7 are set.
3.7
Instant, Individual Block Locking
The instant, individual block locking feature that allows any flash block to be locked or unlocked
with no latency, which enables instant code and data protection.
This locking offers two levels of protection. The first level allows software-only control of block
locking (useful for data blocks that change frequently), while the second level requires hardware
interaction before locking can be changed (useful for code blocks that change infrequently).
The following sections will discuss the operation of the locking system. The term “state [XYZ]”
will be used to specify locking states; e.g., “state [001],” where X = value of WP#, Y = bit DQ
1
of
the Block Lock status register, and Z = bit DQ
0
of the Block Lock status register.
Table 8, “Block
Locking State Transitions” on page 15
defines all of these possible locking states.
Table 6. Flash Memory Status Register Definition
WSMS
ESS
ES
PS
VPPS
PSS
BLS
R
7
6
5
4
3
2
1
0
NOTES:
SR.7 WRITE STATE MACHINE STATUS
1 = Ready (WSMS)
0 = Busy
Check Write State Machine bit first to determine Word Program or
Block Erase completion, before checking Program or Erase Status
bits.
SR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When Erase Suspend is issued, WSM halts execution and sets
both WSMS and ESS bits to “1.” ESS bit remains set to “1” until an
Erase Resume command is issued.
SR.5 = ERASE STATUS (ES)
1 = Error In Block Erase
0 = Successful Block Erase
When this bit is set to “1,” WSM has applied the max. number of
erase pulses and is still unable to verify successful block erasure.
SR.4 = PROGRAM STATUS (PS)
1 = Error in Programming
0 = Successful Programming
When this bit is set to “1,” WSM has attempted but failed to
program a word/byte.
SR.3 = F-V
PP
STATUS (VPPS)
1 = F-V
PP
Low Detect, Operation Abort
0 = F-V
PP
OK
The F-V
status bit does not provide continuous indication of V
level. The WSM interrogates F-V
level only after the Program or
Erase command sequences have been entered, and informs the
system if F-V
has not been switched on. The F-V
is also
checked before the operation is verified by the WSM. The F-V
status bit is not guaranteed to report accurate feedback between
V
PPLK
and V
PP1
min.
SR.2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
When Program Suspend is issued, WSM halts execution and sets
both WSMS and PSS bits to “1.” PSS bit remains set to “1” until a
Program Resume command is issued.
SR.1 = BLOCK LOCK STATUS
1 = Prog/Erase attempted on a locked block; Operation
aborted.
0 = No operation to locked blocks
If a program or erase operation is attempted to one of the locked
blocks, this bit is set by the WSM. The operation specified is
aborted and the device is returned to read status mode.
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
This bit is reserved for future use and should be masked out when
polling the status register.
SR.7 WRITE STATE MACHINE STATUS
1 = Ready (WSMS)
0 = Busy
Check Write State Machine bit first to determine Word Program or
Block Erase completion, before checking Program or Erase Status
bits.
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