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Clocks and Power Control
MOTOROLA
MPC801 USER’S MANUAL
5-7
5
For normal operation, at least one clock source should be active, but you can also configure
both clock sources to be active. In this configuration, EXTCLK provides the oscclk and
oscillator provides the pitrtclk. The input of an unused timing reference should be grounded.
5.3 THE SYSTEM PHASE-LOCKED LOOP
The system PLL performs frequency multiplication and skew elimination and allows the
processor to operate at a high internal clock frequency using a low frequency clock input,
which is a feature with two immediate benefits. Lower frequency clock input reduces the
overall electromagnetic interference generated by the system and oscillating at different
frequencies reduces the cost by eliminating the need to add another oscillator to the system.
The system PLL block diagram is illustrated in Figure 5-3.
Figure 5-3. System PLL Block Diagram
5.3.1 Multiplying the Frequency
The PLL can multiply the input frequency by any integer between 1 and 4,096. The
multiplication factor can be changed by changing the value of the MF bits in the PLL
low-power and reset control register. Even though you can program any integer value from
1 to 4,096, the resulting VCO output frequency must be in the range specified in
Electrical Characteristics
. As defined in Table 5-5, the multiplication factor is set to a
predetermined value during power-on reset.
Section 20
5.3.2 Eliminating Skew
The PLL is capable of eliminating the skew between the external clock entering the core, the
internal clock phases, and the CLKOUT pin. Therefore, the PLL is useful for tightening
synchronous timings. Skew elimination is only active when the PLL is enabled and
programmed with a multiplication factor of 1 or 2 (MF=0 or 1) and the timing reference to the
system PLL is the external clock input EXTAL. With PLL disabled, the clock skew can be
much larger.
VDDSYN / VSSSYN
PHASE
COMPARATOR
MULT. FACTOR
MF[0:11]
XFC
OSCCLK
UP
DOWN
VCOOUT
FEEDBACK
CLOCK
DELAY
CHARGE
PUMP
VCO