![](http://datasheet.mmic.net.cn/290000/XPC801ZP25_datasheet_16187868/XPC801ZP25_31.png)
Introduction
1-2
MPC801 USER’S MANUAL
MOTOROLA
1
Four Major Power-Saving Modes
— Full on, doze, sleep, and deep sleep
— Gear mode
256-Pin Ball Grid Array Packaging
26-Bit Address Bus and 32-bit Data Bus
— Supports multiple master designs
— Four-beat transfer bursts, two-clock minimum bus transactions
— Dynamic bus sizing controlled by on-chip memory controller
— Supports data parity
— Tolerates 5V inputs and provides 3.3V outputs
Flexible Memory Management
— 8-entry, fully associative instruction translation lookaside buffers (TLBs)
— 8-entry, fully associative data translation lookaside buffers
— 4K, 16K, 512K, or 8M page size support
— 1K protection granularity
— Support for multiple protection groups and tasks
— Attribute support for trapping, writethrough, cache inhibit, and memory-mapped I/O
— Supports software tablewalk
1K Physical Address, Two-Way, Set-Associative Data Cache
— Single-cycle access on hit
— 4-word line size, burst fill, least recently used (LRU) replacement
— Cache lockable on line granularity
— Read capability of all tags and attributes provided for debugging purposes
2K Physical Address, Two-Way, Set-Associative Instruction Cache
— Single-cycle access on hit
— Four-word line size, burst fill, least recently used replacement
— Cache lockable on line granularity
— Cache control supports PowerPC invalidate instruction
— Cache inhibit supported for the entire cache or per memory management unit page
in conjunction with memory management logic
— Read capability of all tags and attributes provided for debugging purposes
Memory Controller with Eight Banks
— Glueless interface to SRAM, DRAM, EPROM, FLASH and other peripherals
— Byte write enables and selectable parity generation
— 32-bit address decodes with bit masks
— Each bank can be a chip-select or RAS to support a DRAM bank
— Maximum of 30 programmable wait states per bank
— Programmable DRAM controller supports most size and speed memory interfaces
— Four CAS lines, four WE lines, and one OE line
— Boot chip-select available at reset (optional 8-, 16-, or 32-bit memory)
— Variable block sizes (32K to 256M)
— Selectable write protection