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Index
MOTOROLA
MPC801 USER’S MANUAL
Index-3
INDEX
load/store unit,
6-25
register unit,
6-15
sequencer unit, 6-4
core control registers,
A-1
counters,
18-18
CR,
2-3
,
13-5
CR_B,
10-11
Crystals,
5-1
CS(0-5),
2-5
CS(2-3),
2-5
current address space ID register,
11-14
D
D(0-31),
2-3
,
13-6
DAR,
6-31
,
7-10
,
18-11
,
18-14
data address register,
18-11
data cache, 10-1
block diagram,
10-2
cache inhibited accesses,
10-9
coherency support,
10-10
control instructions,
10-11
control,
10-10
data cache read,
10-7
data cache write,
10-8
disabling,
10-10
features,
10-1
flushing and invalidation,
10-10
freeze,
10-9
implementation specific operations,
10-3
locking,
10-10
operation,
10-7
organization,
10-2
PowerPC architecture instructions,
10-3
programming model,
10-3
reading,
10-11
registers
special,
10-3
data cache states,
10-7
data MMU registers
access protection,
11-13
CAM entry read,
11-25
control,
11-12
effective page number,
11-18
RAM entry read register 0,
11-26
RAM entry read register 1,
11-27
real page number port,
11-20
tablewalk control,
11-19
data storage interrupt,
7-10
DC electrical specifications,
20-4
dcbf,
7-5
,
10-11
dcbi,
7-5
,
7-7
,
10-11
dcbst,
7-5
,
10-11
dcbt,
7-5
,
10-11
dcbtst,
7-5
,
10-11
dcbz,
7-5
,
10-11
debug enable register,
18-53
debug mode, 18-20
,
18-21
,
18-28
checkstop state,
18-27
entering,
18-24
exceptions,
18-28
exiting,
18-28
registers,
18-51
saving machine state,
18-27
support,
18-22
instruction fetch from the development
port,
9-12
debug mode disable,
7-10
,
18-20
,
18-40
debug mode enable vs debug mode disable,
18-24
debug mode enable,
18-20
debug mode logic implementation
(illustration),
18-23
debug port timing,
20-22
debug port unmaskable interrupt,
6-10
DEC (definition),
12-23
decoding instructions,
19-17
decoding,
18-31
decrementer (DEC),
12-3
,
12-10
decrementer register,
12-23
definitions,
23-1
DER,
18-24
,
18-26
development port, 18-20
,
18-28
decoding,
18-31
pins,
18-29
registers,
18-30
serial communications
clock mode selection,
18-31
debug mode,
18-37
trap enable mode,
18-32
development port shift register,
18-30
development serial data out,
18-29
development support, 18-1
programming model,
18-41
development system interface, 18-20
debug mode support,
18-22
trap enable mode,
18-22
differences between MPC860 and MPC801,
1-8
disabling the data cache,
10-10
divide instructions,
6-24
downloading
end download,
18-40
fast download,
18-39
start download procedure command,
18-40
DP(0-3),
13-6
DP0,
2-3
DP1,
2-4
DP2,
2-4
DP3,
2-4
DPDR,
18-30
DPIR,
18-30