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Index
Index-6
MPC801
USER’S MANUAL
MOTOROLA
INDEX
fixed-point trap,
8-1
move condition register from XER,
8-2
move from external to core,
8-1
move from others,
8-2
move from special registers,
8-1
move to external to the core,
8-1
move to LR, CTR,
8-1
move to special,
8-1
move to/from special purpose register,
8-3
order storage access,
8-3
partially executed,
7-17
sample/preload,
19-18
storage control,
7-7
,
8-3
storage synchronization,
8-2
string,
8-3
synchronize,
8-2
system call,
8-1
timing list,
8-1
integrated circuits,
16-26
interface connection to EDO,
15-52
interface, development system,
18-20
inter-integrated circuit,
16-15
internal memory map register,
3-1
internal pullup resistors,
16-35
interrupt cause register,
18-51
interrupt mechanism,
16-18
interrupts, 6-6
,
7-8
causes,
18-39
classes,
7-8
definitions,
7-8
handling,
18-26
memory managment unit,
11-29
processing,
7-8
recovery,
6-8
sources,
16-3
structure (illustration),
12-4
timing,
6-11
,
20-21
invalid and preferred instructions,
7-1
invalidation,
10-10
IRQ0,
2-4
IRQ1,
2-4
IRQ2,
2-3
IRQ3,
2-3
IRQ4,
2-3
,
2-4
IRQ5,
2-4
,
2-7
IRQ6,
2-4
IRQ7,
2-4
isync,
7-5
IWP(0-1),
2-6
IWP2,
2-7
J
jitter tolerance,
16-5
joint test action group,
19-1
JTAG (definition),
19-1
JTAG reset,
4-3
JTAG timing,
20-26
K
key mechanism,
5-24
KR,
2-3
KR/RETRY,
13-5
KR_B,
10-11
L
L-address,
18-9
LAST,
15-38
LCTRL2,
18-14
,
18-20
L-data,
18-9
level interrupt,
12-6
level signal,
18-28
little endian,
6-29
load & lock,
9-7
,
9-8
load/store
address comparators,
18-17
address,
18-9
data comparators,
18-17
data,
18-9
support AND-OR control register,
18-48
support comparators control register,
18-46
synchronizing instructions,
6-27
load/store unit, 6-25
atomic update primitives,
6-29
block diagram,
6-26
exceptions,
6-31
features,
6-25
instruction issue,
6-26
instruction timing,
6-29
little endian support,
6-29
nonspeculative load instructions,
6-28
off-core special registers access,
6-30
stalling storage control instructions,
6-30
storage control instructions,
6-30
store instruction cycles issue,
6-27
unaligned instructions execution,
6-28
locking the data cache,
10-10
LOOP,
15-31
loss of lock,
4-3
low power mode,
12-15
LRU,
1-2
lwarx,
10-11
LWP0,
2-7
LWP1,
2-7