![](http://datasheet.mmic.net.cn/290000/XPC801ZP25_datasheet_16187868/XPC801ZP25_5.png)
TABLE OF CONTENTS (Continued)
Paragraph
Number
Page
Number
Title
MOTOROLA
MPC801 USER’S MANUAL
vii
6.2.7.1
6.2.8
6.3
6.3.1
6.3.1.1
6.3.1.2
6.3.1.3
6.4
6.4.1
6.5
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
6.5.7
6.5.8
6.5.9
6.5.10
6.5.11
6.5.12
6.5.13
6.5.13.1
Latency .........................................................................6-13
Interrupt Ordering .....................................................................6-13
The Register Unit ...............................................................................6-15
The Control Registers ..............................................................6-15
Physical Location of Special Registers .........................6-19
Bit Assignment of the Control Registers .......................6-20
Initializing the Control Registers ...................................6-24
The Fixed-Point Unit ...........................................................................6-24
Updating XER with Divide Instructions .....................................6-24
The Load/Store Unit ...........................................................................6-25
Load/Store Instruction ..............................................................6-26
Synchronizing Load/Store Instructions .....................................6-27
Instructions Issued to the Data Cache .....................................6-27
Issuing Store Instruction ...........................................................6-27
Nonspeculative Load Instructions ............................................6-28
Executing Unaligned Instructions .............................................6-28
Little-Endian Mode Support ......................................................6-29
Atomic Update Primitives .........................................................6-29
Instruction Timing .....................................................................6-29
Stalling Storage Control Instructions ........................................6-30
Accessing Off-Core Special Registers .....................................6-30
Storage Control Instructions .....................................................6-30
Exception Processing ...............................................................6-31
Using DAR, DSISR, and BAR .......................................6-31
Section 7
PowerPC Architecture Compliance
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.7.1
7.1.7.2
7.1.8
7.1.8.1
7.1.8.2
7.1.9
PowerPC User Instruction Set Architecture (Book I) ............................7-1
Computation Modes ...................................................................7-1
Reserved Fields .........................................................................7-1
Classes of Instructions ...............................................................7-1
Exceptions ..................................................................................7-2
The Branch Processor ................................................................7-2
Fetching Instructions ..................................................................7-2
Branch Instructions .....................................................................7-2
Invalid Branch Instruction Forms ....................................7-2
Branch Prediction ...........................................................7-2
The Fixed-Point Processor .........................................................7-2
Move To/From System Register Instructions ..................7-3
Fixed-Point Arithmetic Instructions .................................7-3
The Load/Store Processor .........................................................7-3