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Memory Controller
MOTOROLA
MPC801 USER’S MANUAL
15-73
15
SCY—Cycle Length in Clocks
These bits determine the number of wait states inserted in the cycle when the
general-purpose chip-select machine handles the external memory access and it is the main
parameter for determining the cycle’s length. The total cycle length may vary, depending on
the settings of other timing attributes. The total memory access length is (2 + SCY)
If an external TA response has been selected for this memory bank (by setting the SETA
bit), then SCY[0:3] bits are not used. Be aware that following a system reset, these bits are
set to 1111 in OR0.
×
clocks
0000 = 0 clock cycle wait state.
0001 = 1 clock cycle wait state.
0010 = 2 clock cycle wait states.
0011 = 3 clock cycle wait states.
0100 = 4 clock cycle wait states.
0101 = 5 clock cycle wait states.
0110 = 6 clock cycle wait states.
0111 = 7 clock cycle wait states.
1000 = 8 clock cycle wait states.
1001 = 9 clock cycle wait states.
1010 = 10 clock cycle wait states.
1011 = 11 clock cycle wait states.
1100 = 12 clock cycle wait states.
1101 = 13 clock cycle wait states.
1110 = 14 clock cycle wait states.
1111 = 15 clock cycle wait states.
SETA—External Transfer Acknowledge
This bit specifies when the TA signal is externally generated once the GPCM is selected to
handle the memory access that was initiated to this memory region. Be aware that following
a system reset, this bit is reset in OR0.
0 = TA
1 = TA
is internally generated by the memory controller, unless asserted earlier.
is generated by external logic.
TRLX—Timing Relaxed
When this bit is asserted, it modifies the timing of the signals controlling the memory devices
once the GPCM is selected to handle the memory access that was initiated to this memory
region. Be aware that following a system reset, this bit is set in OR0.
0 = Normal timing is generated by the GPCM.
1 = Relaxed timing is generated by the GPCM.