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| 型號： | VG36646141BT-8 |
| 廠商： | Vanguard International Semiconductor Corporation |
| 英文描述： | CMOS Synchronous Dynamic RAM |
| 中文描述： | 同步動態(tài)隨機(jī)存儲器的CMOS |
| 文件頁數(shù)： | 5/70頁 |
| 文件大小： | 974K |
| 代理商： | VG36646141BT-8 |
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Document : 1G5-0127
Rev2
Page 5
VIS
Preliminary VG36641641BT
CMOS Synchronous Dynamic RAM
Notes:
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test Conditions
VG36641641B
-8
Min
-7
Unit
Notes
Min
Max
130
130
Max
130
130
Operating current
I
CC1
Burst length = 1
One bank active
t
RC
t
RC(MIN.)
, Io = 0mA
CKE V
IH(MAX.)
t
CK
= 10ns
I
CC
2PSCKE V
IH(MAX.)
t
CK
=
I
CC
2N
CKE
V
IH(MIN.)
t
CK
= 10ns.
V
IH(MIN.)
Input signals are changed one
time during 2 CLK cycles.
I
CC
2NSCKE
V
IH(MIN.)
, tCK =
CLK V
IL(MAX.)
Input signals are stable.
I
CC
3P
CKE V
IL(MAX.)
, t
CK
= 10ns
I
CC
3PSCKE V
IL(MAX.)
, t
CK
=
I
CC
3N
CKE
V
IH(MAX.)
, t
CK
= 10ns
V
IH(MIN.)
Input signals are changed
one time during 2CLKs.
I
CC
3NSCKE
V
IH(MIN.)
t
CK
=
CLE
V
IL
(MAX.)
Input signals are stable.
I
CC4
t
CK(MIN.)
, Io = 0mA
All banks Active
I
CC5
t
RC
t
RC(MIN.)
I
CC6
CKE 0.2V
I
LI
0, V
IN
V
DD
+ 0.3V
Pins not under test = 0V
I
LO
V
0, V
OUT
V
DD
(MAX)
DQ# in H - Z., Dout disabled
V
OL
I
OL
= 2mA
V
OH
I
OH
= -2mA
CL = 3
CL = 2
mA
1
Precharge standby
current in power
down mode
Precharge standby current
in Nonpower down mode
I
CC
2P
2
2
mA
2
2
25
25
mA
7
7
Active standby current in
power down mode
7
7
mA
5
5
Active standby current in
Nonpower down mode
40
40
mA
20
20
Operating current
(Burst mode)
CL = 3
CL = 2
170
135
220
170
120
200
mA
2
Refresh current
mA
3
Self refresh current
1
1
mA
Input leakage current
- 5
5
-5
5
Output leakage current
- 5
5
-5
5
Output Low Voltage
Output High Voltage
0.4
0.4
mA
mA
4
4
2.4
2.4
≥
∞
CKE
≥
V
≥
∞
≥
∞
CKE
≥
≥
≤
∞
CKE
V
≥
≥
CKE
≥
μ
A
CKE
≥
μ
A
1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output
open. In addition to this, ICC1 is measured on condition that addresses are changed only one
time during t
CK(MIN.)
.
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output
open. In addition to this, ICC4 is measured on condition that addresses are changed only one
time during t
CK(MIN.)
.
3. ICC5 is measured on condition that addresses are changed only one time during t
CK(MIN.)
.
4. For LVTTL compatible, VG36648041.
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| VG36648041BT-8L | x8 SDRAM |
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| VG4616322BQ-5 | 262,144x32x2-Bit CMOS Synchronous Graphic RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VG36648041BT-10 | 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM |
| VG36648041BT-7 | 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM |
| VG36648041BT-8 | 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM |
| VG36648041BT-8H | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
| VG36648041BT-8L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
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