參數(shù)資料
型號(hào): VG36646141BT-8
廠商: Vanguard International Semiconductor Corporation
英文描述: CMOS Synchronous Dynamic RAM
中文描述: 同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器的CMOS
文件頁(yè)數(shù): 15/70頁(yè)
文件大?。?/td> 974K
代理商: VG36646141BT-8
Document : 1G5-0127
Rev2
Page 15
VIS
Preliminary VG36641641BT
CMOS Synchronous Dynamic RAM
5.1 Burst Length and Sequence
(Burst of Two)
(Burst of Four)
(Burst of Eight)
Full page burst is an extension of the above tables of Sequential Addressing, with the length being 512
for 8M x 8 devices.
Starting Address
(column address A0, binary)
Sequential Addressing
Sequence (decimal)
Interleave Addressing Sequence (decimal)
0
0, 1
0, 1
1
1, 0
1, 0
Starting Address
(column address A1 - A0, binary)
Sequential Addressing
Sequence (decimal)
Interleave Addressing Sequence (decimal)
00
0, 1, 2, 3
0, 1, 2, 3
01
1, 2, 3, 0
1, 0, 3, 2
10
2, 3, 0, 1
2, 3, 0, 1
11
3, 0, 1, 2
3, 2, 1, 0
Starting Address
(column address A2 - A0, binary)
Sequential Addressing
Sequence (decimal)
Interleave Addressing Sequence(decimal)
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
011
3, 4, 5, 6, 7, 0, 1 ,2
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6 ,7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7 ,0 ,1 ,2 ,3 ,4 ,5
6, 7, 4, 5, 2, 3, 0, 1
111
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
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