參數(shù)資料
型號： TMS320C6713BGDPA200
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FLOATING-POINT DIGITAL SIGNAL PROCESSORS
中文描述： 浮點數(shù)字信號處理器
文件頁數(shù)： 80/150頁
文件大?。?/td> 2039K
代理商： TMS320C6713BGDPA200
TMS320C6713, TMS320C6713B
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS186I
DECEMBER 2001
REVISED MAY 2004
80
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
PLL and PLL controller (continued)
Table 41. PLL Wrapper Divider x Registers (PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3)
[0x01B7 C114, 0x01B7 C118, 0x01B7 C11C, and 0x01B7 C120, respectively]
31
28
27
24
23
20
19
16
Reserved
R
0
15
14
12
11
8
7
5
4
3
2
1
0
DxEN
Reserved
PLLDIVx
R/W
1
R
0
R/W
x xxxx
Legend:
R = Read only, R/W = Read/Write; -n = value after reset
Default values for the PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 bits are /1 (0 0000), /1 (0 0000), /2 (0 0001), and /2 (0 0001), respectively.
CAUTION:
D1 and D2 should never be disabled. D3 should only be disabled if ECLKIN is used.
Table 42. PLL Wrapper Divider x Registers (Prescaler Divider D0 and Post-Scaler Dividers D1,
D2, and D3) Description
BIT #
31:16
NAME
Reserved
DESCRIPTION
Reserved. Read-only, writes have no effect.
Divider Dx Enable (where x denotes 0 through 3).
0
–
Divider x Disabled. No clock output.
1
Divider x Enabled (default).
15
DxEN
These divider-enable bits are device-specific and must be set to 1 to enable.
14:5
Reserved
Reserved. Read-only, writes have no effect.
PLL Divider Ratio [Default values for the PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 bits are /1, /1,
/2, and /2, respectively].
4:0
PLLDIVx
00000 =
00001 =
00010 =
00011
00100 =
00101 =
00110
00111
01000 =
01001 =
01010 =
01011
01100
01101
01110
01111
/1
/2
/3
/4
/5
/6
/7
/8
/9
/10
/11
/12
/13
/14
/15
/16
10000 =
10001 =
10010 =
10011
10100 =
10101 =
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
/17
/18
/19
/20
/21
/22
/23
/24
/25
/26
/27
/28
/29
/30
/31
/32
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
Note that SYSCLK2
must
run at half the rate of SYSCLK1. Therefore, the divider ratio of D2 must be two times slower than D1. For example,
if D1 is set to /2, then D2
must
be set to /4.
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