
TMS320C6713, TMS320C6713B
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS186I
DECEMBER 2001
REVISED MAY 2004
48
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
Terminal Functions (Continued)
SIGNAL
NAME
PIN NO.
PYP
TYPE
IPD/
IPU
DESCRIPTION
GDP
HOST-PORT INTERFACE (HPI) (CONTINUED)
HD15/GP[15]
174
B14
IPU
Host-port data pins (
I/O/Z
) [default] or general-purpose input/output pins
(I/O/Z)
Used for transfer of data, address, and control
Also controls initialization of DSP modes at reset via pullup/pulldown
resistors
HD14/GP[14]
173
C14
IPU
Device Endian Mode (HD8)
0
–
Big Endian
1
Little Endian
For a
C6713BGDP
:
Big Endian Mode Correctness EMIFBE (HD12) [C6713
B
only]
0
–
The EMIF data will always be presented on the ED[7:0] side of the
bus, regardless of the endianess mode (Little/Big Endian).
1
In Little Endian mode (HD8 =1), the 8-bit or 16-bit EMIF data will be
present on the ED[7:0] side of the bus.
In Big Endian mode (HD8 =0), the 8-bit or 16-bit EMIF data will be
present on the ED[31:24] side of the bus [default].
HD13/GP[13]
172
A15
IPU
HD12/GP[12]
168
C15
IPU
For a
C6713BPYP
, when Big Endian mode is selected (LENDIAN = 0), for
proper device operation the EMIFBE pin
must
be externally pulled low.
p p
HD11/GP[11]
167
A16
I/O/Z
IPU
This enhancement is
not
supported on the C6713 device. For proper
C6713
device operation,
do not
oppose the internal pullup (IPU) resistor on this pin.
This new functionality does
not
affect systems using the current default value of
HD12=1. For more detailed information on the big endian mode correctness,
see the
EMIF Big Endian Mode Correctness [C6713B Only]
portion of this data
sheet.
HD10/GP[10]
166
B16
IPU
Boot mode (HD[4:3])
00 –
CE1 width 32-bit, HPI boot/Emulation boot
01 –
CE1 width 8-bit, Asynchronous external ROM boot with default
CE1 width 8 bit, Asynchronous external ROM boot with default
timings (default mode)
10
CE1 width 16-bit, Asynchronous external ROM boot with default
timings
11
CE1 width 32-bit, Asynchronous external ROM boot with default
timings
HD9/GP[9]
165
C16
IPU
HD8/GP[8]
160
B17
IPU
HPI_EN (HD14)
0
–
HPI disabled, McASP1 enabled
1
HPI enabled, McASP1 disabled (default)
Other HD pins (HD [15, 13:9, 7:5, 2:0] for 13
or
HD [13, 11:9, 7:5, 2:0] for 13B)
have pullups/pulldowns (IPUs/IPDs). For proper device operation of the HD[15,
13:9, 7, 1, 0] for 13
or
HD[13, 11:9, 7, 1, 0] for 13B,
do not
oppose these pins with
external IPUs/IPDs at reset; however, the HD[6, 5, 2] for 13
or
HD[15, 6, 5, 2] for
13B pins
can
be opposed and driven at reset. For more details, see the Device
Configurations section of this data sheet.
HD7/GP[3]
164
A18
IPU
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. [These IPD/IPU signal pins feature a 13-k
resistor (approximate) for the IPD or 18-k
resistor
(approximate) for the IPU. An external pullup or pulldown resistor no greater than 4.4 k
and 2.0 k
, respectively, should be used to pull a signal
to the opposite supply rail.]