參數(shù)資料
型號： TMS320C6713BGDPA200
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FLOATING-POINT DIGITAL SIGNAL PROCESSORS
中文描述： 浮點(diǎn)數(shù)字信號處理器
文件頁數(shù)： 133/150頁
文件大?。?/td> 2039K
代理商： TMS320C6713BGDPA200
TMS320C6713, TMS320C6713B
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS186I
DECEMBER 2001
REVISED MAY 2004
133
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING
timing requirements for McBSP
(see Figure 57)
NO.
PYPA
167
PYP
200
GDPA
200
GDP
225
GDP
300
UNIT
MIN
2P
§
MAX
2
3
t
c(CKRX)
t
w(CKRX)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
ns
ns
0.5 * t
c(CKRX)
1
5
t
su(FRH-CKRL)
Setup time external FSR high before CLKR low
Setup time, external FSR high before CLKR low
9
1
6
3
8
0
3
4
9
1
6
3
ns
6
t
h(CKRL-FRH)
Hold time external FSR high after CLKR low
Hold time, external FSR high after CLKR low
ns
7
t
su(DRV-CKRL)
Setup time DR valid before CLKR low
Setup time, DR valid before CLKR low
ns
8
t
h(CKRL-DRV)
Hold time DR valid after CLKR low
Hold time, DR valid after CLKR low
ns
10
t
su(FXH-CKXL)
Setup time external FSX high before CLKX low
Setup time, external FSX high before CLKX low
ns
11
t
h(CKXL-FXH)
Hold time external FSX high after CLKX low
Hold time, external FSX high after CLKX low
ns
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
§
The minimum CLKR/X period is twice the CPU cycle time (2P) and not faster than 75 Mbps (13.3 ns). This means that the maximum bit rate for
communications between the McBSP and other devices is 75 Mbps for 167-MHz and 225-MHz CPU clocks or 50 Mbps for 100-MHz CPU clock;
where the McBSP is either the master or the slave. Care must be taken to ensure that the AC timings specified in this data sheet are met. The
maximum bit rate for McBSP-to-McBSP communications is 67 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle
time (2P), or 15 ns (67 MHz), whichever value is larger. For example, when running parts at 150 MHz (P = 6.7 ns), use 15 ns as the minimum
CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P =
33 ns (30 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port
is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM
= 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave.
This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the resonable range of 40/60 duty cycle.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMS320C6713BGDP-C20 制造商:Texas Instruments 功能描述:
TMS320C6713BPYP167 制造商:TI 功能描述:_
TMS320C6713BPYP200 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Floating-Pt Dig Sig Processors RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320C6713BPYP225 制造商:Texas Instruments 功能描述:
TMS320C6713BZDP225 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Floating-Pt Dig Sig Processors RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
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