參數(shù)資料
型號(hào): TMS320C6713BGDPA200
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: FLOATING-POINT DIGITAL SIGNAL PROCESSORS
中文描述: 浮點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù): 121/150頁
文件大?。?/td> 2039K
代理商: TMS320C6713BGDPA200
TMS320C6713, TMS320C6713B
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS186I
DECEMBER 2001
REVISED MAY 2004
121
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
RESET TIMING (CONTINUED)
Phase 1
Phase 2
12
11
10
9
8
7
6
5
4
3
14
13
2
1
CLKIN
ECLKIN
Internal Reset
Internal SYSCLK1
Internal SYSCLK2
Internal SYSCLK3
CLKOUT3
RESET
Phase 3
EMIF Z Group
EMIF Low Group
Z Group 1
Z Group 2
Boot and Device
Configuration Pins
EMIF Z group consists of:
2
2
2
2
6713 ECLKOUT
§
6713 CLKOUT2
§
6713B ECLKOUT
§
6713B CLKOUT2
§
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE and
HOLDA
EMIF low group consists of: BUSREQ
Z group 1 consists of:
CLKR0/ACLKR0, CLKR1/AXR0[6], CLKX0/ACLKX0, CLKX1/AMUTE0, FSR0/AFSR0, FSR1/AXR0[7],
FSX0/AFSX0, FSX1, DX0/AXR0[1], DX1/AXR0[5], TOUT0/AXR0[2], TOUT1/AXR0[4], SDA0 and SCL0.
Z group 2 consists of:
All other HPI, McASP0/1, GPIO, and I2C1 signals.
Boot and device configurations consist of: HD[14, 8, 4:3].
Figure 47. Reset Timing
Reset Phase 1
: The RESET pin is asserted. During this time, all internal clocks are running at the CLKIN
frequency divide-by-8. The CPU is also running at the CLKIN frequency divide-by-8.
Reset Phase 2
: The RESET pin is deasserted but the internal reset is stretched. During this time, all internal
clocks are running at the CLKIN frequency divide-by-8. The CPU is also running at the CLKIN frequency
divide-by-8.
Reset Phase 3
: Both the RESET pin and internal reset are deasserted. During this time, all internal clocks are
running at their default divide-down frequency of CLKIN. The CPU clock (SYSCLK1) is running at CLKIN
frequency. The peripheral clock (SYSCLK2) is running at CLKIN frequency divide-by-2. The EMIF internal clock
source (SYSCLK3) is running at CLKIN frequency divide-by-2. SYSCLK3 is reflected on the ECLKOUT pin
(when EKSRC bit = 0 [default]). CLKOUT3 is running at CLKIN frequency divide-by-8.
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