參數(shù)資料
型號: TMS320C6713BGDPA200
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: FLOATING-POINT DIGITAL SIGNAL PROCESSORS
中文描述: 浮點數(shù)字信號處理器
文件頁數(shù): 55/150頁
文件大?。?/td> 2039K
代理商: TMS320C6713BGDPA200
TMS320C6713, TMS320C6713B
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS186I
DECEMBER 2001
REVISED MAY 2004
55
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
Terminal Functions (Continued)
SIGNAL
NAME
PIN NO.
PYP
TYPE
IPD/
IPU
DESCRIPTION
GDP
GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
HD15/GP[15]
174
B14
IPU
Host-port data pins (
I/O/Z
) [default] or general-purpose input/output pins
(I/O/Z) and some function as boot configuration pins at reset.
Used for transfer of data, address, and control
Also controls initialization of DSP modes at reset via pullup/pulldown
resistors
HD14/GP[14]
173
C14
IPU
HD13/GP[13]
172
A15
IPU
HD12/GP[12]
168
C15
I/O/Z
IPU
As general-purpose input/output (GP[x]) functions, these pins are software-con-
figurable through registers. The “GPxEN” bits in the GP Enable register and the
GPxDIR bits in the GP Direction register must be properly configured:
HD11/GP[11]
167
A16
IPU
GPxEN = 1; GP[x] pin is enabled.
GPxDIR = 0; GP[x] pin is an input.
GPxDIR = 1; GP[x] pin is an output.
HD10/GP[10]
166
B16
IPU
HD9/GP[9]
165
C16
IPU
For the functionality description of the Host-port data pins or the boot configura-
For the functionality description of the Host port data pins or the boot configura
tion pins, see the Host-Port Interface (HPI) portion of this table.
HD8/GP[8]
160
B17
IPU
GP[7](EXT_INT7)
7
E3
General-purpose input/output pins (
I/O/Z
) which also function as external
interrupts
Edge-driven
Polarity independently selected via the External Interrupt Polarity Register
bits (EXTPOL.[3:0])
GP[6](EXT_INT6)
2
D2
GP[5](EXT_INT5)/
AMUTEIN0
6
C1
I/O/Z
IPU
GP[4] and GP[5] pins also function as AMUTEIN1 McASP1 mute input and
AMUTEIN0 McASP0 mute input, respectively, if enabled by the INEN bit in the
associated McASP AMUTE register.
Host-port data pin 7 (
I/O/Z
) [default] or general-purpose input/output pin 3
(I/O/Z)
d GP[5] i
l
AMUTEIN1 M ASP1
t i
GP[4](EXT_INT4)/
AMUTEIN1
1
C2
HD7/GP[3]
164
A18
I/O/Z
IPU
CLKOUT2/GP[2]
82
Y12
I/O/Z
IPD
Clock output at half of device speed (
O/Z
) [default] or this pin can be
programmed as GP[2] pin.
HINT/GP[1]
135
J20
O
IPU
Host interrupt (from DSP to host) (
O
) [default] or this pin can be programmed as
a GP[1] pin (I/O/Z).
HD4/GP[0]
156
C19
I/O/Z
IPD
Host-port data pin 4 (
I/O/Z
) [ default] or this pin can be programmed as a GP[0]
pin (I/O/Z).
RESERVED FOR TEST
IPU
Reserved. (Leave unconnected,
do
not
connect to power or ground)
Reserved. (Leave unconnected,
do
not
connect to power or ground)
Reserved. (Leave unconnected,
do
not
connect to power or ground)
IPD
Reserved. (Leave unconnected,
do
not
connect to power or ground)
Reserved. This pin does
not
have an IPU. For proper C6713/13B device
operation, the D12 pin
must
be externally pulled down with a 10-k
resistor.
RSV
RSV
RSV
RSV
198
200
179
A5
B5
C12
D7
O/Z
A
§
O
O/Z
RSV
178
D12
I
RSV
RSV
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. [These IPD/IPU signal pins feature a 13-k
resistor (approximate) for the IPD or 18-k
resistor
(approximate) for the IPU. An external pullup or pulldown resistor no greater than 4.4 k
and 2.0 k
, respectively, should be used to pull a signal
to the opposite supply rail.]
§
A = Analog signal
181
180
A12
B11
Reserved. (Leave unconnected,
do
not
connect to power or ground)
Reserved. (Leave unconnected,
do
not
connect to power or ground)
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