參數(shù)資料
型號： TMS320C6713BGDPA200
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FLOATING-POINT DIGITAL SIGNAL PROCESSORS
中文描述： 浮點(diǎn)數(shù)字信號處理器
文件頁數(shù)： 46/150頁
文件大?。?/td> 2039K
代理商： TMS320C6713BGDPA200
TMS320C6713, TMS320C6713B
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS186I
DECEMBER 2001
REVISED MAY 2004
46
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
TERMINAL FUNCTIONS
The terminal functions table identifies the external signal names, the associated pin (ball) numbers along with
the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal
pullup/pulldown resistors and a functional pin description. For more detailed information on device
configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see the Device
Configurations section of this data sheet.
Terminal Functions
SIGNAL
NAME
PIN NO.
PYP
TYPE
IPD/
IPU
DESCRIPTION
GDP
CLOCK/PLL CONFIGURATION
IPD
Clock Input
Clock output at half of device speed (
O/Z
) [default] (SYSCLK2 internal signal
from the clock generator) or this pin can be programmed as GP[2] pin (I/O/Z)
CLKIN
204
A3
I
CLKOUT2/GP[2]
82
Y12
O/Z
IPD
CLKOUT3
184
D10
O
IPD
Clock output programmable by OSCDIV1 register in the PLL controller.
Clock generator input clock source select
0
Reserved, do not use.
1
–
CLKIN square wave [default]
For proper device operation, this pin must be either left unconnected or
externally pulled up with a 1-k
resistor.
CLKMODE0
205
C4
I
IPU
PLLHV
202
C5
A
§
Analog power (3.3 V) for PLL (PLL Filter)
JTAG EMULATION
JTAG test-port mode select
JTAG test-port data out
JTAG test-port data in
JTAG test-port clock
JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the
IEEE 1149.1
JTAG Compatibility Statement
section of this data sheet.
TMS
TDO
TDI
TCK
192
187
191
193
B7
A8
A7
A6
I
IPU
IPU
IPU
IPU
O/Z
I
I
TRST
197
B6
I
IPD
EMU5
EMU4
EMU3
EMU2
—
—
—
—
B12
C11
B10
D3
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPU
IPU
IPU
IPU
Emulation pin 5. Reserved for future use, leave unconnected.
Emulation pin 4. Reserved for future use, leave unconnected.
Emulation pin 3. Reserved for future use, leave unconnected.
Emulation pin 2. Reserved for future use, leave unconnected.
EMU1
EMU0
185
186
B9
D9
I/O/Z
IPU
Emulation [1:0] pins
Select the device functional mode of operation
EMU[1:0]
Operation
00
Boundary Scan/Functional Mode (see Note)
01
Reserved
10
Reserved
11
Emulation/Functional Mode [default] (see the
IEEE 1149.1
JTAG Compatibility Statement
section of this data sheet)
The DSP can be placed in Functional mode when the EMU[1:0] pins are
configured for either Boundary Scan or Emulation.
Note: When the EMU[1:0] pins are configured for Boundary Scan mode, the
internal pulldown (IPD) on the TRST signal must
not
be opposed in order to
operate in Functional mode.
For the Boundary Scan mode drive EMU[1:0]
and
RESET pins low.
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. [These IPD/IPU signal pins feature a 13-k
resistor (approximate) for the IPD or 18-k
resistor
(approximate) for the IPU. An external pullup or pulldown resistor no greater than 4.4 k
and 2.0 k
, respectively, should be used to pull a signal
to the opposite supply rail.]
§
A = Analog signal
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMS320C6713BGDP-C20 制造商:Texas Instruments 功能描述:
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TMS320C6713BPYP225 制造商:Texas Instruments 功能描述:
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