參數(shù)資料
型號： TMS320C6713BGDPA200
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FLOATING-POINT DIGITAL SIGNAL PROCESSORS
中文描述： 浮點數(shù)字信號處理器
文件頁數(shù)： 36/150頁
文件大?。?/td> 2039K
代理商： TMS320C6713BGDPA200
TMS320C6713, TMS320C6713B
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS186I
DECEMBER 2001
REVISED MAY 2004
36
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
DEVICE CONFIGURATIONS (CONTINUED)
Table 23. C6713/13B Device Multiplexed/Shared Pins
MULTIPLEXED PINS
DEFAULT
FUNCTION
DEFAULT SETTING
DESCRIPTION
NAME
PYP
GDP
CLKOUT2/GP[2]
82
Y12
CLKOUT2
GP2EN = 0
(GPEN register bit)
GP[2] function disabled,
CLKOUT2 enabled
When the CLKOUT2 pin is enabled,
the CLK2EN bit in the EMIF global
control register (GBLCTL) controls the
CLKOUT2 pin.
CLK2EN = 0:
CLKOUT2 held high
CLK2EN = 1:
CLKOUT2 enabled
to clock [default]
To use these software-configurable
GPIO pins, the GPxEN bits in the GP
Enable Register and the GPxDIR bits
in the GP Direction Register must be
properly configured.
GPxEN = 1:
GP[x] pin enabled
GPxDIR = 0:
GP[x] pin is an input
GPxDIR = 1:
GP[x] pin is an
output
GP[5](EXT_INT5)/AMUTEIN0
GP[4](EXT_INT4)/AMUTEIN1
6
1
C1
C2
GP[5](EXT_INT5)
GP[4](EXT_INT4)
No Function
GPxDIR = 0 (input)
GP5EN = 0 (disabled)
GP4EN = 0 (disabled)
[(GPEN register bits)
GP[x] function disabled]
To use AMUTEIN0/1 pin function, the
GP[5]/GP[4] pins must be configured
as an input, the INEN bit set to 1, and
the polarity through the INPOL bit
selected in the associated McASP
AMUTE register.
CLKS0/AHCLKR0
DR0/AXR0[0]
DX0/AXR0[1]
FSR0/AFSR0
FSX0/AFSX0
CLKR0/ACLKR0
CLKX0/ACLKX0
28
27
20
24
21
19
16
K3
J1
H2
J3
H1
H3
G3
By default McBSP0 peripheral pins are
By default, McBSP0 peripheral pins are
enabled upon reset (McASP0 pins are
disabled).
MCBSP0DIS = 0
(DEVCFG register bit)
McASP0 pins disabled
McASP0 pins disabled,
McBSP0 pins enabled
bi )
McBSP0 pin function
To enable the McASP0 peripheral pins,
the MCBSP0DIS bit in the DEVCFG
register must be set to 1 (disabling the
M BSP0
i h
l i
McBSP0 peripheral pins).
CLKS1/SCL1
8
E1
By default, McBSP1 peripheral pins are
enabled upon reset (I2C1 and McASP0
pins are disabled)
pins are disabled).
DR1/SDA1
37
M2
MCBSP1DIS = 0
(DEVCFG register bit)
I2C1 and McASP0 pins
disabled, McBSP1 pins
enabled
DX1/AXR0[5]
32
L2
McBSP1 pin function
FSR1/AXR0[7]
38
M3
To enable the I2C1 and McASP0
peripheral pins the MCBSP1DIS bit in
peripheral pins, the MCBSP1DIS bit in
the DEVCFG register must be set to 1
(disabling the McBSP1 peripheral pins).
CLKR1/AXR0[6]
36
M1
CLKX1/AMUTE0
33
L3
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