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參數(shù)資料
| 型號： | TMS320C6713BGDPA200 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | FLOATING-POINT DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 浮點數(shù)字信號處理器 |
| 文件頁數(shù)： | 77/150頁 |
| 文件大?。?/td> | 2039K |
| 代理商： | TMS320C6713BGDPA200 |
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TMS320C6713, TMS320C6713B
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS186I
DECEMBER 2001
REVISED MAY 2004
77
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
PLL and PLL controller (continued)
Table 36. PLL Clock Frequency Ranges
CLOCK SIGNAL
GDP-225
GDPA-200
PYP-200
PYPA-167
UNIT
MIN
12
140
MAX
100
600
PLLREF (PLLEN = 1)
PLLOUT
SYSCLK1
SYSCLK3 (EKSRC = 0)
AUXCLK
MHz
MHz
MHz
MHz
MHz
Device Speed (DSP Core)
100
50
§
SYSCLK2 rate
must
be exactly half of SYSCLK1.
Also see the electrical specification (timing requirements and switching characteristics parameters) in the input and output clocks section of this
data sheet.
§
When the McASP module is
not
used, the AUXCLK maximum frequency can be any frequency up to the CLKIN maximum frequency.
The EMIF itself may be clocked by an external reference clock via the ECLKIN pin or can be generated on-chip
as SYSCLK3. SYSCLK3 is derived from divider D3 off of PLLOUT (see Figure 15, PLL and Clock Generator
Logic). The EMIF clock selection is programmable via the EKSRC bit in the DEVCFG register.
The settings for the PLL multiplier and each of the dividers in the clock generation block may be reconfigured
via software at run time. If either the input to the PLL changes due to D0, CLKMODE0, or CLKIN, or if the PLL
multiplier is changed, then software must enter bypass first and stay in bypass until the PLL has had enough
time to lock (see electrical specifications). For the programming procedure, see the
TMS320C6000 DSP
Software-Programmable Phase-Locked Loop (PLL) Controller Reference Guide
(literature number SPRU233).
SYSCLK2 is the internal clock source for peripheral bus control. SYSCLK2 (Divider D2)
must
be programmed
to be half of the SYSCLK1 rate. For example, if D1 is configured to divide-by-2 mode (/2), then D2
must
be
programmed to divide-by-4 mode (/4). SYSCLK2 is also tied directly to CLKOUT2 pin (see Figure 15).
During the programming transition of Divider D1 and Divider D2 (resulting in SYSCLK1 and SYSCLK2 output
clocks, see Figure 15), the order of programming the PLLDIV1 and PLLDIV2 registers must be observed to
ensure that SYSCLK2 always runs at half the SYSCLK1 rate or slower. For example, if the divider ratios of D1
and D2 are to be changed from /1, /2 (respectively) to /5, /10 (respectively) then, the PLLDIV2 register must be
programmed before the PLLDIV1 register. The transition ratios become /1, /2; /1, /10; and then /5, /10. If the
divider ratios of D1 and D2 are to be changed from /3, /6 to /1, /2 then, the PLLDIV1 register must be programmed
before the PLLDIV2 register. The transition ratios, for this case, become /3, /6; /1, /6; and then /1, /2. The final
SYSCLK2 rate
must
be exactly half of the SYSCLK1 rate.
Note that Divider D1 and Divider D2 must
always
be enabled (i. e., D1EN and D2EN bits are set to “1” in the
PLLDIV1 and PLLDIV2 registers).
The PLL Controller registers should be modified only by the CPU or via emulation. The HPI should
not
be used
to directly access the PLL Controller registers.
For detailed information on the clock generator (PLL Controller registers) and their associated software bit
descriptions, see Table 38 through Table 44.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TMS320C6713BGDP-C20 | 制造商:Texas Instruments 功能描述: |
| TMS320C6713BPYP167 | 制造商:TI 功能描述:_ |
| TMS320C6713BPYP200 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Floating-Pt Dig Sig Processors RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| TMS320C6713BPYP225 | 制造商:Texas Instruments 功能描述: |
| TMS320C6713BZDP225 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Floating-Pt Dig Sig Processors RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
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