參數(shù)資料
型號： TMS320C6713BGDPA200
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FLOATING-POINT DIGITAL SIGNAL PROCESSORS
中文描述： 浮點數(shù)字信號處理器
文件頁數(shù)： 67/150頁
文件大?。?/td> 2039K
代理商： TMS320C6713BGDPA200
TMS320C6713, TMS320C6713B
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS186I
DECEMBER 2001
REVISED MAY 2004
67
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
CPU CSR register description (continued)
Table 25. CPU CSR Register Bit Field Description
BIT #
NAME
DESCRIPTION
31:24
CPU ID
CPU ID + REV ID. Read only.
Identifies which CPU is used and defines the silicon revision of the CPU.
23:16
REVISION ID
CPU ID + REVISION ID (31:16) are combined for a value of:
0x0203
for C6713/13B
Control power-down modes. The values are always read as zero.
15:10
PWRD
000000
001001
010001
011010
011100
Others
=
=
=
=
=
=
no power-down (default)
PD1, wake-up by an enabled interrupt
PD1, wake-up by an enabled or not enabled interrupt
PD2, wake-up by a device reset
PD3, wake-up by a device reset
Reserved
9
SAT
Saturate bit.
Set when any unit performs a saturate. This bit can be cleared only by the MVC instruction and can
be set only by a functional unit. The set by the a functional unit has priority over a clear (by the MVC
instruction) if they occur on the same cycle. The saturate bit is set one full cycle (one delay slot) after
a saturate occurs. This bit will not be modified by a conditional instruction whose condition is false.
8
EN
Endian bit. This bit is read-only.
Depicts the device endian mode.
0
=
Big Endian mode.
1
=
Little Endian mode [default].
Program Cache control mode.
L1D, Level 1 Program Cache
000/010 =
All other PCC values reserved.
Data Cache control mode.
L1D, Level 1 Data Cache
000/010 =
All other DCC values reserved
Previous GIE (global interrupt enable); saves the Global Interrupt Enable (GIE) when an interrupt is
taken. Allows for proper nesting of interrupts.
7:5
PCC
Cache Enabled / Cache accessed and updated on reads.
4:2
DCC
Cache Enabled / 2-Way Cache
1
PGIE
0
1
=
=
Previous GIE value is 0. (default)
Previous GIE value is 1.
0
GIE
Global interrupt enable bit.
Enables (1) or disables (0) all interrupts except the reset interrupt and NMI (nonmaskable interrupt).
0
1
=
=
Disables all interrupts (except the reset interrupt and NMI) [default]
Enables all interrupts (except the reset interrupt and NMI)
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相關代理商/技術參數(shù)
參數(shù)描述
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