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TMS320C6713, TMS320C6713B
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS186I
DECEMBER 2001
REVISED MAY 2004
1
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
Highest-Performance Floating-Point Digital
Signal Processors (DSPs): C6713/C6713B
Eight 32-Bit Instructions/Cycle
32/64-Bit Data Word
300-, 225-, 200-MHz (GDP), and 200-,
167-MHz (PYP) Clock Rates
3.3-, 4.4-, 5-, 6-Instruction Cycle Times
2400/1800, 1800 /1350 , 1600 /1200 , and
1336 /1000 MIPS /MFLOPS
Rich Peripheral Set, Optimized for Audio
Highly Optimized C/C++ Compiler
Advanced Very Long Instruction Word
(VLIW) TMS320C67x
DSP Core
Eight Independent Functional Units:
Two ALUs (Fixed-Point)
Four ALUs (Floating- and Fixed-Point)
Two Multipliers (Floating- and
Fixed-Point)
Load-Store Architecture With 32 32-Bit
General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
Instruction Set Features
Native Instructions for IEEE 754
Single- and Double-Precision
Byte-Addressable (8-, 16-, 32-Bit Data)
8-Bit Overflow Protection
Saturation; Bit-Field Extract, Set, Clear;
Bit-Counting; Normalization
L1/L2 Memory Architecture
4K-Byte L1P Program Cache
(Direct-Mapped)
4K-Byte L1D Data Cache (2-Way)
256K-Byte L2 Memory Total: 64K-Byte
L2 Unified Cache/Mapped RAM, and
192K-Byte Additional L2 Mapped RAM
Device Configuration
Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
Endianness: Little Endian, Big Endian
32-Bit External Memory Interface (EMIF)
Glueless Interface to SRAM, EPROM,
Flash, SBSRAM, and SDRAM
512M-Byte Total Addressable External
Memory Space
Enhanced Direct-Memory-Access (EDMA)
Controller (16 Independent Channels)
16-Bit Host-Port Interface (HPI)
Two Multichannel Audio Serial Ports
(McASPs)
Two Independent Clock Zones Each
(1 TX and 1 RX)
Eight Serial Data Pins Per Port:
Individually Assignable to any of the
Clock Zones
Each Clock Zone Includes:
Programmable Clock Generator
Programmable Frame Sync Generator
TDM Streams From 2-32 Time Slots
Support for Slot Size:
8, 12, 16, 20, 24, 28, 32 Bits
Data Formatter for Bit Manipulation
Wide Variety of I2S and Similar Bit
Stream Formats
Integrated Digital Audio Interface
Transmitter (DIT) Supports:
S/PDIF, IEC60958-1, AES-3, CP-430
Formats
Up to 16 transmit pins
Enhanced Channel Status/User Data
Extensive Error Checking and Recovery
Two Inter-Integrated Circuit Bus (I
2
C Bus
)
Multi-Master and Slave Interfaces
Two Multichannel Buffered Serial Ports:
Serial-Peripheral-Interface (SPI)
High-Speed TDM Interface
AC97 Interface
Two 32-Bit General-Purpose Timers
Dedicated GPIO Module With 16 pins
(External Interrupt Capable)
Flexible Phase-Locked-Loop (PLL) Based
Clock Generator Module
IEEE-1149.1 (JTAG
)
Boundary-Scan-Compatible
Package Options:
208-Pin PowerPAD
Plastic (Low-Profile)
Quad Flatpack (PYP)
272-Ball, Ball Grid Array Package (GDP)
0.13-
μ
m/6-Level Copper Metal Process
CMOS Technology
3.3-V I/Os, 1.2
-V Internal (GDP & PYP)
3.3-V I/Os, 1.4-V Internal (GDP) (300 MHz
only)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320C67x and PowerPAD are trademarks of Texas Instruments.
I
2
C Bus is a trademark of Philips Electronics N.V. Corporation
All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
These values are compatible with existing 1.26V designs.
This document contains information on products in more than one phase
of development. The status of each device is indicated on the page(s)
specifying its electrical characteristics.
Copyright
2004, Texas Instruments Incorporated