
Section 1 Overview
Rev. 1.00 Sep. 13, 2007 Page 10 of 1076
REJ09B0364-0100
1.4
Pin Assignments
1.4.1
Pin Assignments
PK7/PO31/TIOCA11/TIOCB11
PK6/PO30/TIOCA11
PK5/PO29/TIOCA10/TIOCB10
PJ5/PO21/TIOCA7/TIOCB7/TCLKG
PJ4/PO20/TIOCA7
PJ3/PO19/TIOCC6/TIOCD6/TCLKF
PJ2/PO18/TIOCC6/TCLKE
PK4/PO28/TIOCA10
PK3/PO27/TIOCC9/TIOCD9
PK2/PO26/TIOCC9
PK1/PO25/TIOCA9/TIOCB9
PK0/PO24/TIOCA9
PJ7/PO23/TIOCA8/TIOCB8/TCLKH
PJ6/PO22/TIOCA8
PJ0/PO16/TIOCA6
PJ1/PO17/TIOCA6/TIOCB6
*1
PB1/
CS1
/CS2
-B/
CS5
-A/
CS6
-B/
CS7
-B
PB2/
CS2
-A/
CS6
-A
PB3/
CS3
/CS7
-A
MD2
PF7/SCK5/A23/
CS4
-C/
CS5
-C/
CS6
-C/
CS7
-C
PF6/RxD5/IrRxD/A22/
CS6
-D
PF5/TxD5/IrTxD/A21/
CS5
-D
PF4/A20
PF3/A19
Vss
PF2/A18
PF1/A17
PF0/A16
PE7/A15
PE6/A14
PE5/A13
Vss
PE4/A12
Vcc
PE3/A11
PE2/A10
PE1/A9
PE0/A8
PD7/A7
PD6/A6
Vss
PD5/A5
PD4/A4
PD3/A3
PD2/A2
P61/TMCI2/RxD4/
TEND2
/IRQ9
-B
P60/TMRI2/TxD4/
DREQ2
/IRQ8
-B
STBY P17/TCLKD-B/SCL0/
ADTRG1
/IRQ7
-A
P16/TCLKC-B/SCK3/SDA0/
DACK1
-A/
IRQ6
-A
Vcc
EXTAL
XTAL
Vss
WDTOVF
/TDO
P15/TCLKB-B/RxD3/SCL1/
TEND1
-A/
IRQ5
-A
P14/TCLKA-B/TxD3/SDA1/
DREQ1
-A/
IRQ4
-A
VCL
RES Vss P13/
ADTRG0
/IRQ3
-A
P12/SCK2/
DACK0
-A/
IRQ2
-A
P11/RxD2/
TEND0
-A/
IRQ1
-A
P10/TxD2/
DREQ0
-A/
IRQ0
-A
PI7/D15
PI6/D14
PI5/D13
PI4/D12
Vss
PI3/D11
PI2/D10
PI1/D9
PI0/D8
Vcc
PH7/D7
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
P62/TMO2/SCK4/
DACK2/IRQ10-B/TRST
PLLVcc
P63/TMRI3/TxD6/
DREQ3/IRQ11-B/TMS
PLLVss
P64/TMCI3/RxD6/
TEND3/IRQ12-B/TDI
P65/TMO3/SCK6/
DACK3/IRQ13-B/TCK
MD0
P50/AN0/
IRQ0-B
P51/AN1/
IRQ1-B
P52/AN2/
IRQ2-B
Avcc
P53/AN3/
IRQ3-B
Avss
P54/AN4/
IRQ4-B
Vref
P55/AN5/
IRQ5-B
P56/AN6/DA0/
IRQ6-B
P57/AN7/DA1/
IRQ7-B
MD1
PA0/
BREQO/BS-A
PA1/
BACK/(RD/WR)
PA2/
BREQ/WAIT
PA3/
LLWR/LLB
PA4/
LHWR/LUB
PA5/
RD
PA6/
AS/AH/BS-B
Vss
PA7/B
φ
Vcc
PB0/
CS0/CS4-A/CS5-B
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
PH6/D6
PH5/D5
PH4/D4
Vss
PH3/D3
PH2/D2
PH1/D1
PH0/D0
NMI
P37/PO15/TIOCA2/TIOCB2/TCLKD-A
P36/PO14/TIOCA2
P35/PO13/TIOCA1/TIOCB1/TCLKC-A/
DACK1-B
P34/PO12/TIOCA1/
TEND1-B
P33/PO11/TIOCC0/TIOCD0/TCLKB-A/
DREQ1-B
P32/PO10/TIOCC0/TCLKA-A/
DACK0-B
P31/PO9/TIOCA0/TIOCB0/
TEND0-B
Vcc
P30/PO8/TIOCA0/
DREQ0-B
Vss
P27/PO7/TIOCA5/TIOCB5/
IRQ15
P26/PO6/TIOCA5/TMO1/TxD1/
IRQ14
P25/PO5/TIOCA4/TMCI1/RxD1/
IRQ13-A
P24/PO4/TIOCA4/TIOCB4/TMRI1/SCK1/
IRQ12-A
P23/PO3/TIOCC3/TIOCD3/
IRQ11-A
P22/PO2/TIOCC3/TMO0/TxD0/
IRQ10-A
P21/PO1/TIOCA3/TMCI0/RxD0/
IRQ9-A
P20/PO0/TIOCA3/TIOCB3/TMRI0/SCK0/
IRQ8-A
EMLE*2
PD0/A0
PD1/A1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LQFP-120
(Top View)
Note: 1. In single-chip mode prots D and E can be used (initial state). Pin functions are selectable by setting the PCJKE bit in PFCRD.
Pin functions are selectable by setting the PCJKE bit in PFCRD. Ports D and E are enabled when PCJKE = 0 (initial value)
and ports J and K are enabled when PCJKE = 1. In external extended mode, only ports D and E can be used.
2. This pin is an on-chip emulator enable pin. Drive this pin low for the connection in normal operating mode.
The on-chip emulator function is enabled by driving this pin high. When the on-chip emulator is in use, the P62, P63,
P64, P65, and
WDTOVF pins are dedicated pins for the on-chip emulator. For details on a connection example with the E10A,
see E10A Emulator User's Manual.
Figure 1.3 Pin Assignments