
Rev. 1.00 Sep. 13, 2007 Page 1070 of 1076
REJ09B0364-0100
CPU priority control function over DTC
and DMAC ............................................. 136
CRC Operation Circuit ........................... 718
Crystal resonator..................................... 914
Cycle stealing mode................................ 296
D
D/A converter ......................................... 789
Data direction register ............................ 381
Data register............................................ 382
Data transfer controller (DTC) ............... 337
Direct convention ................................... 697
DMA controller (DMAC)....................... 259
Double-buffered structure....................... 672
Download pass/fail result parameter....... 818
DTC vector address ................................ 349
DTC vector address offset ...................... 349
Dual address mode.................................. 285
E
Endian and data alignment ..................... 199
Endian format ......................................... 191
Error protection ...................................... 854
Error signal ............................................. 697
Exception handling................................... 87
Exception-handling state .......................... 66
Extended repeat area............................... 283
Extended repeat area function ................ 298
Extension of chip select (
CS) assertion
period...................................................... 212
External access bus................................. 180
External bus............................................ 185
External bus clock (B
φ) .................. 181, 909
External bus interface ............................. 190
External clock......................................... 915
External interrupts .................................. 119
F
Flash erase block select parameter.......... 827
Flash memory ......................................... 797
Flash multipurpose address area
parameter ................................................ 825
Flash multipurpose data destination
parameter ................................................ 826
Flash pass and fail parameter.................. 819
Flash program/erase frequency parameter
........................................................ 823, 837
Free-running count operation.................. 499
Frequency divider ........................... 909, 916
Full address mode ................................... 347
Full-scale error........................................ 782
G
General illegal instructions ....................... 99
H
Hardware protection ............................... 853
Hardware standby mode ................. 920, 960
I
I/O ports .................................................. 373
I2C bus format......................................... 741
I2C bus interface2 (IIC2)......................... 725
ID code.................................................... 683
Idle cycle................................................. 238
Illegal instruction ...................................... 99
Input buffer control register .................... 383
Input capture function............................. 502
Internal interrupts.................................... 120
Internal peripheral bus ............................ 180
Internal system bus ................................. 180
Interrupt .................................................... 96
Interrupt control mode 0 ......................... 127
Interrupt control mode 2 ......................... 129