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型號：	R5F61634N50FPV
元件分類：	微控制器/微處理器
英文描述：	32-BIT, FLASH, 50 MHz, MICROCONTROLLER, PQFP120
封裝：	14 X 14 MM, 0.40 MM PITCH, LEAD FREE, PLASTIC, LQFP-120
文件頁數(shù)：	358/1108頁
文件大?。?/td>	6716K
代理商：	R5F61634N50FPV

DMA Controller (DMAC)

Rev. 1.00 Sep. 13, 2007 Page 294 of 1076

REJ09B0364-0100

Activation Sources

The DMAC is activated by an auto request, an on-chip module interrupt, and an external request.

The activation source is specified by bits DTF1 and DTF0 in DMDR.

Activation by Auto Request

The auto request activation is used when a transfer request from an external device or an on-chip

peripheral module is not generated such as a transfer between memory and memory or between

memory and an on-chip peripheral module which does not request a transfer. A transfer request is

automatically generated inside the DMAC. In auto request activation, setting the DTE bit in

DMDR starts a transfer. The bus mode can be selected from cycle stealing and burst modes.

Activation by On-Chip Module Interrupt

An interrupt request from an on-chip peripheral module (on-chip peripheral module interrupt) is

used as a transfer request. When a DMA transfer is enabled (DTE = 1), the DMA transfer is

started by an on-chip module interrupt.

The activation source of the on-chip module interrupt is selected by the DMA module request

select register (DMRSR). The activation sources are specified to the individual channels. Table

9.5 is a list of on-chip module interrupts for the DMAC. The interrupt request selected as the

activation source can generate an interrupt request simultaneously to the CPU or DTC. For details,

refer to section 6, Interrupt Controller.

The DMAC receives interrupt requests by on-chip peripheral modules independent of the interrupt

controller. Therefore, the DMAC is not affected by priority given in the interrupt controller.

When the DMAC is activated while DTA = 1, the interrupt request flag is automatically cleared by

a DMA transfer. If multiple channels use a single transfer request as an activation source, when

the channel having priority is activated, the interrupt request flag is cleared. In this case, other

channels may not be activated because the transfer request is not held in the DMAC.

When the DMAC is activated while DTA = 0, the interrupt request flag is not cleared by the

DMAC and should be cleared by the CPU or DTC transfer.

When an activation source is selected while DTE = 0, the activation source does not request a

transfer to the DMAC. It requests an interrupt to the CPU or DTC.

In addition, make sure that an interrupt request flag as an on-chip module interrupt source is

cleared to 0 before writing 1 to the DTE bit.

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