
Rev. 1.00 Sep. 13, 2007 Page xxii of xxviii
16.10 Usage Notes ...................................................................................................................... 713
16.10.1
Module Stop State Setting ................................................................................ 713
16.10.2
Break Detection and Processing ....................................................................... 713
16.10.3
Mark State and Break Detection ....................................................................... 713
16.10.4
Receive Error Flags and Transmit Operations
(Clock Synchronous Mode Only) ..................................................................... 713
16.10.5
Relation between Writing to TDR and TDRE Flag .......................................... 714
16.10.6
Restrictions on Using DTC or DMAC.............................................................. 714
16.10.7
SCI Operations during Power-Down State ....................................................... 715
16.11 CRC Operation Circuit ..................................................................................................... 718
16.11.1
Features............................................................................................................. 718
16.11.2
Register Descriptions........................................................................................ 719
16.11.3
CRC Operation Circuit Operation .................................................................... 721
16.11.4
Note on CRC Operation Circuit........................................................................ 724
Section 17 I
2C Bus Interface 2 (IIC2)..................................................................725
17.1
Features............................................................................................................................. 725
17.2
Input/Output Pins.............................................................................................................. 727
17.3
Register Descriptions........................................................................................................ 728
17.3.1
I
2C Bus Control Register A (ICCRA) ............................................................... 729
17.3.2
I
2C Bus Control Register B (ICCRB) ............................................................... 730
17.3.3
I
2C Bus Mode Register (ICMR)........................................................................ 732
17.3.4
I
2C Bus Interrupt Enable Register (ICIER)....................................................... 733
17.3.5
I
2C Bus Status Register (ICSR)......................................................................... 736
17.3.6
Slave Address Register (SAR).......................................................................... 739
17.3.7
I
2C Bus Transmit Data Register (ICDRT) ........................................................ 740
17.3.8
I
2C Bus Receive Data Register (ICDRR).......................................................... 740
17.3.9
I
2C Bus Shift Register (ICDRS)........................................................................ 740
17.4
Operation .......................................................................................................................... 741
17.4.1
I
2C Bus Format.................................................................................................. 741
17.4.2
Master Transmit Operation ............................................................................... 742
17.4.3
Master Receive Operation ................................................................................ 744
17.4.4
Slave Transmit Operation ................................................................................. 746
17.4.5
Slave Receive Operation................................................................................... 749
17.4.6
Noise Canceler.................................................................................................. 750
17.4.7
Example of Use................................................................................................. 751
17.5
Interrupt Request .............................................................................................................. 755
17.6
Bit Synchronous Circuit.................................................................................................... 755
17.7
Usage Notes ...................................................................................................................... 756