
Rev. 1.00 Sep. 13, 2007 Page xviii of xxviii
12.4
Operation .......................................................................................................................... 498
12.4.1
Basic Functions................................................................................................. 498
12.4.2
Synchronous Operation..................................................................................... 504
12.4.3
Buffer Operation ............................................................................................... 506
12.4.4
Cascaded Operation .......................................................................................... 510
12.4.5
PWM Modes..................................................................................................... 512
12.4.6
Phase Counting Mode....................................................................................... 517
12.5
Interrupt Sources...............................................................................................................524
12.6
DTC Activation ................................................................................................................ 526
12.7
DMAC Activation ............................................................................................................ 526
12.8
A/D Converter Activation................................................................................................. 526
12.9
Operation Timing.............................................................................................................. 527
12.9.1
Input/Output Timing ......................................................................................... 527
12.9.2
Interrupt Signal Timing .................................................................................... 531
12.10 Usage Notes ...................................................................................................................... 535
12.10.1
Module Stop Function Setting .......................................................................... 535
12.10.2
Input Clock Restrictions ................................................................................... 535
12.10.3
Caution on Cycle Setting .................................................................................. 536
12.10.4
Conflict between TCNT Write and Clear Operations....................................... 536
12.10.5
Conflict between TCNT Write and Increment Operations ............................... 537
12.10.6
Conflict between TGR Write and Compare Match........................................... 537
12.10.7
Conflict between Buffer Register Write and Compare Match .......................... 538
12.10.8
Conflict between TGR Read and Input Capture ............................................... 538
12.10.9
Conflict between TGR Write and Input Capture .............................................. 539
12.10.10 Conflict between Buffer Register Write and Input Capture.............................. 540
12.10.11 Conflict between Overflow/Underflow and Counter Clearing ......................... 541
12.10.12 Conflict between TCNT Write and Overflow/Underflow ................................ 541
12.10.13 Multiplexing of I/O Pins ................................................................................... 542
12.10.14 PPG1 Setting when TPU1 Pin is Used.............................................................. 542
12.10.15 Interrupts and Module Stop Mode .................................................................... 542
Section 13 Programmable Pulse Generator (PPG) .............................................. 543
13.1
Features............................................................................................................................. 543
13.2
Input/Output Pins.............................................................................................................. 546
13.3
Register Descriptions........................................................................................................ 548
13.3.1
Next Data Enable Registers H, L (NDERH, NDERL) ..................................... 549
13.3.2
Output Data Registers H, L (PODRH, PODRL)............................................... 552
13.3.3
Next Data Registers H, L (NDRH, NDRL) ...................................................... 554
13.3.4
PPG Output Control Register (PCR) ................................................................ 559
13.3.5
PPG Output Mode Register (PMR) .................................................................. 561