
Rev. 1.00 Sep. 13, 2007 Page 1071 of 1076
REJ09B0364-0100
Interrupt controller.................................. 103
Interrupt exception handling sequence ... 131
Interrupt exception handling vector table 121
Interrupt response times.......................... 132
Interrupt sources ..................................... 119
Interrupt sources and vector address
offsets ..................................................... 121
Interval timer .......................................... 620
Interval timer mode................................. 620
Inverse convention.................................. 698
IRQn interrupts ....................................... 119
J
JTAG interface ....................................... 759
L
Little endian............................................ 191
M
Mark state ....................................... 672, 713
Master receive mode............................... 744
Master transmit mode ............................. 742
MCU operating modes.............................. 67
Memory MAT configuration .................. 802
Mode 2...................................................... 72
Mode 4...................................................... 72
Mode 5...................................................... 73
Mode 6...................................................... 73
Mode 7...................................................... 73
Mode pin................................................... 67
Multi-clock mode ................................... 941
Multiprocessor bit................................... 683
Multiprocessor communication
function................................................... 683
N
NMI interrupt.......................................... 119
Noise canceler......................................... 750
Nonlinearity error.................................... 782
Non-overlapping pulse output................. 569
Normal transfer mode ............................. 357
Normal transfer mode ............................. 289
Number of Access Cycles ....................... 192
O
Offset addition ........................................ 301
Offset error.............................................. 782
On-board programming .......................... 829
On-board programming mode................. 797
On-chip baud rate generator.................... 675
On-chip ROM disabled extended mode.... 67
On-chip ROM enabled extended mode..... 67
Open-drain control register ..................... 385
Oscillator................................................. 914
Output buffer control .............................. 385
Output trigger.......................................... 568
Overflow ......................................... 604, 618
P
Package dimensions .................... 1065, 1066
Parity bit.................................................. 672
Periodic count operation ......................... 499
Peripheral module clock (P
φ).......... 181, 909
Phase counting mode .............................. 517
Pin assignments......................................... 10
Pin functions ............................................. 16
PLL circuit ...................................... 909, 915
Port function controller ........................... 433
Port register............................................. 382
Power-down modes................................. 919
Procedure program.................................. 847
Processing states ....................................... 66
Product lineup ....................................... 1064