
Rev. 1.00 Sep. 13, 2007 Page 1074 of 1076
REJ09B0364-0100
TGR .........................495, 983, 1003, 1019
TIER ........................490, 982, 1002, 1018
TIOR........................472, 982, 1002, 1018
TMDR .....................470, 982, 1002, 1018
TSR............................................. 491, 634
TSR (TPU).......................982, 1003, 1018
TSTR .......................496, 982, 1002, 1018
TSYR.......................497, 982, 1002, 1018
VBR...................................................... 37
WTCRA.....................161, 977, 996, 1013
WTCRB.....................161, 977, 996, 1013
Repeat transfer mode ...................... 290, 358
Reset ......................................................... 90
Reset state................................................. 66
Resolution............................................... 782
S
Sample-and-hold circuit ......................... 777
Scan mode .............................................. 774
Serial communication interface (SCI) .... 625
Short address mode................................. 347
Single address mode ............................... 286
Single mode............................................ 773
Slave receive mode................................. 749
Slave transmit mode ............................... 746
Sleep instruction exception handling........ 98
Sleep mode ..................................... 920, 942
Slot illegal instructions ............................. 99
Smart card interface................................ 696
Software protection................................. 854
Software standby mode .................. 920, 944
Space state .............................................. 672
Stack status after exception handling...... 100
Standard serial communication interface
specifications for boot mode................... 860
Start bit ................................................... 672
State transition of TAP controller........... 905
State transitions ........................................ 66
Stop bit ................................................... 672
Strobe assert/negate timing ..................... 193
Synchronous clearing.............................. 504
Synchronous operation............................ 504
Synchronous presetting........................... 504
System clock (I
φ)............................ 181, 909
T
TAP controller ........................................ 905
Toggle output.......................................... 501
Trace exception handling.......................... 93
Transfer information ............................... 347
Transfer information read skip function . 356
Transfer information writeback skip
function ................................................... 357
Transfer modes ....................................... 289
Transmit/receive data.............................. 672
Trap instruction exception handling ......... 97
U
User boot MAT....................................... 802
User boot mode............................... 800, 843
User break controller (UBC)................... 143
User MAT............................................... 802
User program mode ........................ 800, 833
V
Vector table address.................................. 88
Vector table address offset........................ 88
W
Wait control ............................................ 209
Watchdog timer (WDT).......................... 613
Watchdog timer mode............................. 618
Waveform output by compare match...... 500
Write data buffer function....................... 252