
Rev. 1.00 Sep. 13, 2007 Page xx of xxviii
14.7.2
A/D Converter Activation................................................................................. 606
14.8
Usage Notes ...................................................................................................................... 607
14.8.1
Notes on Setting Cycle ..................................................................................... 607
14.8.2
Conflict between TCNT Write and Counter Clear ........................................... 607
14.8.3
Conflict between TCNT Write and Increment.................................................. 608
14.8.4
Conflict between TCOR Write and Compare Match ........................................ 608
14.8.5
Conflict between Compare Matches A and B................................................... 609
14.8.6
Switching of Internal Clocks and TCNT Operation ......................................... 609
14.8.7
Mode Setting with Cascaded Connection ......................................................... 611
14.8.8
Module Stop State Setting ................................................................................ 611
14.8.9
Interrupts in Module Stop State ........................................................................ 611
Section 15 Watchdog Timer (WDT) ................................................................... 613
15.1
Features............................................................................................................................. 613
15.2
Input/Output Pin ............................................................................................................... 614
15.3
Register Descriptions........................................................................................................ 615
15.3.1
Timer Counter (TCNT)..................................................................................... 615
15.3.2
Timer Control/Status Register (TCSR)............................................................. 615
15.3.3
Reset Control/Status Register (RSTCSR)......................................................... 617
15.4
Operation .......................................................................................................................... 618
15.4.1
Watchdog Timer Mode..................................................................................... 618
15.4.2
Interval Timer Mode......................................................................................... 620
15.5
Interrupt Source ................................................................................................................620
15.6
Usage Notes ...................................................................................................................... 621
15.6.1
Notes on Register Access ................................................................................. 621
15.6.2
Conflict between Timer Counter (TCNT) Write and Increment....................... 622
15.6.3
Changing Values of Bits CKS2 to CKS0.......................................................... 622
15.6.4
Switching between Watchdog Timer Mode and Interval Timer Mode............. 622
15.6.5
Internal Reset in Watchdog Timer Mode.......................................................... 623
15.6.6
System Reset by
WDTOVF Signal................................................................... 623
15.6.7
Transition to Watchdog Timer Mode or Software Standby Mode.................... 623
Section 16 Serial Communication Interface (SCI, IrDA, CRC) ......................... 625
16.1
Features............................................................................................................................. 625
16.2
Input/Output Pins.............................................................................................................. 630
16.3
Register Descriptions........................................................................................................ 631
16.3.1
Receive Shift Register (RSR) ........................................................................... 633
16.3.2
Receive Data Register (RDR)........................................................................... 633
16.3.3
Transmit Data Register (TDR).......................................................................... 634
16.3.4
Transmit Shift Register (TSR) .......................................................................... 634