
Rev. 1.00 Sep. 13, 2007 Page 1069 of 1076
REJ09B0364-0100
Index
Numerics
0 output/1 output..................................... 501
0-output/1-output .................................... 501
16-bit access space.................................. 200
16-bit counter mode................................ 604
16-bit timer pulse unit (TPU) ................. 451
8-bit access space.................................... 199
8-bit timers (TMR) ................................. 579
A
A/D conversion accuracy........................ 782
Absolute accuracy................................... 782
Acknowledge.......................................... 741
Address error ............................................ 94
Address map ............................................. 74
Address modes........................................ 285
Address/data multiplexed
I/O interface.................................... 193, 228
All-module-clock-stop mode .......... 920, 943
Area 0 ..................................................... 194
Area 1 ..................................................... 195
Area 2 ..................................................... 195
Area 3 ..................................................... 196
Area 4 ..................................................... 196
Area 5 ..................................................... 197
Area 6 ..................................................... 198
Area 7 ..................................................... 198
Area division........................................... 188
Asynchronous mode ............................... 672
AT-cut parallel-resonance type............... 914
Available output signal and settings
in each port ............................................. 424
Average transfer rate generator............... 626
B
B
φ clock output control...........................965
Basic bus interface .......................... 192, 202
Big endian ............................................... 191
Bit rate..................................................... 654
Bit synchronous circuit ........................... 755
Block structure........................................ 803
Block transfer mode........................ 291, 360
Boot mode....................................... 800, 829
Boundary scan commands ...................... 895
Buffer operation ...................................... 506
Burst access mode................................... 297
Burst ROM interface....................... 192, 223
Bus access modes.................................... 296
Bus arbitration......................................... 254
Bus configuration.................................... 180
Bus controller (BSC)............................... 155
Bus cycle division ................................... 354
Bus width ................................................ 191
Bus-released state...................................... 66
Byte control SRAM interface ......... 192, 215
C
Cascaded connection............................... 604
Cascaded operation ................................. 510
Chain transfer.......................................... 361
Chip select signals................................... 189
Clock pulse generator ............................. 909
Clock synchronization cycle (Tsy).......... 182
Clocked synchronous mode .................... 689
Communications protocol....................... 862
Compare match A ................................... 602
Compare match B ................................... 603
Compare match count mode ................... 605
Compare match signal............................. 602
Counter operation.................................... 498