
Rev. 1.00 Sep. 13, 2007 Page xxiv of xxviii
21.2
Mode Transition Diagram................................................................................................. 800
21.3
Memory MAT Configuration ........................................................................................... 802
21.4
Block Structure .................................................................................................................803
21.4.1
Block Diagram of H8SX/1632.......................................................................... 803
21.4.2
Block Diagram of H8SX/1634.......................................................................... 804
21.4.3
Block Diagram of H8SX/1638.......................................................................... 805
21.5
Programming/Erasing Interface ........................................................................................ 806
21.6
Input/Output Pins.............................................................................................................. 808
21.7
Register Descriptions........................................................................................................ 808
21.7.1
Programming/Erasing Interface Registers ........................................................ 809
21.7.2
Programming/Erasing Interface Parameters ..................................................... 816
21.7.3
RAM Emulation Register (RAMER)................................................................ 828
21.8
On-Board Programming Mode ......................................................................................... 829
21.8.1
Boot Mode ........................................................................................................ 829
21.8.2
User Program Mode.......................................................................................... 833
21.8.3
User Boot Mode................................................................................................ 843
21.8.4
On-Chip Program and Storable Area for Program Data ................................... 847
21.9
Protection.......................................................................................................................... 853
21.9.1
Hardware Protection ......................................................................................... 853
21.9.2
Software Protection........................................................................................... 854
21.9.3
Error Protection ................................................................................................ 854
21.10 Flash Memory Emulation Using RAM............................................................................. 856
21.11 Switching between User MAT and User Boot MAT........................................................ 859
21.12 Programmer Mode ............................................................................................................ 860
21.13 Standard Serial Communication Interface Specifications for Boot Mode ........................ 860
21.14 Usage Notes ...................................................................................................................... 889
Section 22 Boundary Scan................................................................................... 891
22.1
Features............................................................................................................................. 891
22.2
Block Diagram of Boundary Scan Function ..................................................................... 892
22.3
Pin Configuration.............................................................................................................. 892
22.4
Register Descriptions........................................................................................................ 893
22.4.1
Instruction Register (JTIR) ............................................................................... 894
22.4.2
Bypass Register (JTBPR) ................................................................................. 895
22.4.3
Boundary Scan Register (JTBSR) .................................................................... 896
22.4.4
IDCODE Register (JTID) ................................................................................. 904
22.5
Operations......................................................................................................................... 905
22.5.1
TAP Controller ................................................................................................. 905
22.5.2
Commands ........................................................................................................ 905
22.6
Usage Notes ...................................................................................................................... 907