
Rev. 1.00 Sep. 13, 2007 Page xxvi of xxviii
24.8.3
Pin State on Exit from Deep Software Standby Mode...................................... 950
24.8.4
B
φ Operation after Exit from Deep Software Standby Mode ........................... 951
24.8.5
Setting Oscillation Settling Time after Exit
from Deep Software Standby Mode.................................................................. 952
24.8.6
Deep Software Standby Mode Application Example ....................................... 954
24.8.7
Flowchart of Deep Software Standby Mode Operation .................................... 958
24.9
Hardware Standby Mode .................................................................................................. 960
24.9.1
Transition to Hardware Standby Mode............................................................. 960
24.9.2
Clearing Hardware Standby Mode.................................................................... 960
24.9.3
Hardware Standby Mode Timing...................................................................... 960
24.9.4
Timing Sequence at Power-On ......................................................................... 961
24.10 Sleep Instruction Exception Handling .............................................................................. 962
24.11
Βφ Clock Output Control.................................................................................................. 965
24.12 Usage Notes ...................................................................................................................... 966
24.12.1
I/O Port Status................................................................................................... 966
24.12.2
Current Consumption during Oscillation Settling Standby Period ................... 966
24.12.3
Module Stop State of DMAC or DTC .............................................................. 966
24.12.4
On-Chip Peripheral Module Interrupts ............................................................. 966
24.12.5
Writing to MSTPCRA, MSTPCRB, and MSTPCRC ....................................... 966
24.12.6
Control of Input Buffers by DIRQnE (n = 3 to 0)............................................. 967
24.12.7
Input Buffer Control by DIRQnE (n = 3 to 0) .................................................. 967
24.12.8
B
φ Output State ................................................................................................ 967
Section 25 List of Registers................................................................................. 969
25.1
Register Addresses (Address Order)................................................................................. 970
25.2
Register Bits ..................................................................................................................... 985
25.3
Register States in Each Operating Mode ........................................................................ 1005
Section 26 Electrical Characteristics ................................................................. 1021
26.1
Absolute Maximum Ratings ........................................................................................... 1021
26.2
DC Characteristics .......................................................................................................... 1022
26.3
AC Characteristics .......................................................................................................... 1025
26.3.1
Clock Timing .................................................................................................. 1025
26.3.2
Control Signal Timing .................................................................................... 1028
26.3.3
Bus Timing ..................................................................................................... 1029
26.3.4
DMAC Timing................................................................................................ 1044
26.3.5
Timing of On-Chip Peripheral Modules ......................................................... 1047
26.4
A/D Conversion Characteristics ..................................................................................... 1055
26.5
D/A Conversion Characteristics ..................................................................................... 1055
26.6
Flash Memory Characteristics ........................................................................................ 1056