
Rev. 1.00 Sep. 13, 2007 Page xi of xxviii
4.3
Register Descriptions .......................................................................................................... 83
4.3.1
Reset Status Register (RSTSR)........................................................................... 83
4.3.2
Reset Control/Status Register (RSTCSR)........................................................... 84
4.4
Pin Reset ............................................................................................................................. 85
4.5
Deep Software Standby Reset............................................................................................. 85
4.6
Watchdog Timer Reset ....................................................................................................... 85
4.7
Determination of Reset Generation Source......................................................................... 85
Section 5 Exception Handling ...............................................................................87
5.1
Exception Handling Types and Priority.............................................................................. 87
5.2
Exception Sources and Exception Handling Vector Table ................................................. 88
5.3
Reset ................................................................................................................................... 90
5.3.1
Reset Exception Handling................................................................................... 90
5.3.2
Interrupts after Reset........................................................................................... 91
5.3.3
On-Chip Peripheral Functions after Reset Release ............................................. 91
5.4
Traces.................................................................................................................................. 93
5.5
Address Error...................................................................................................................... 94
5.5.1
Address Error Source.......................................................................................... 94
5.5.2
Address Error Exception Handling ..................................................................... 95
5.6
Interrupts............................................................................................................................. 96
5.6.1
Interrupt Sources................................................................................................. 96
5.6.2
Interrupt Exception Handling ............................................................................. 97
5.7
Instruction Exception Handling .......................................................................................... 97
5.7.1
Trap Instruction................................................................................................... 97
5.7.2
Sleep Instruction Exception Handling ................................................................ 98
5.7.3
Exception Handling by Illegal Instruction .......................................................... 99
5.8
Stack Status after Exception Handling.............................................................................. 100
5.9
Usage Note........................................................................................................................ 101
Section 6 Interrupt Controller ..............................................................................103
6.1
Features............................................................................................................................. 103
6.2
Input/Output Pins.............................................................................................................. 105
6.3
Register Descriptions ........................................................................................................ 105
6.3.1
Interrupt Control Register (INTCR) ................................................................. 106
6.3.2
CPU Priority Control Register (CPUPCR) ....................................................... 107
6.3.3
Interrupt Priority Registers A to I, K to O, Q, and R (IPRA to IPRI,
IPRK to IPRO, IPRQ, and IPRR) ..................................................................... 108
6.3.4
IRQ Enable Register (IER) ............................................................................... 110
6.3.5
IRQ Sense Control Registers H and L (ISCRH, ISCRL).................................. 112
6.3.6
IRQ Status Register (ISR)................................................................................. 117