
Rev. 1.00 Sep. 13, 2007 Page xii of xxviii
6.3.7
Software Standby Release IRQ Enable Register (SSIER) ................................ 118
6.4
Interrupt Sources...............................................................................................................119
6.4.1
External Interrupts ............................................................................................ 119
6.4.2
Internal Interrupts ............................................................................................. 120
6.5
Interrupt Exception Handling Vector Table...................................................................... 121
6.6
Interrupt Control Modes and Interrupt Operation............................................................. 127
6.6.1
Interrupt Control Mode 0 .................................................................................. 127
6.6.2
Interrupt Control Mode 2 .................................................................................. 129
6.6.3
Interrupt Exception Handling Sequence ........................................................... 131
6.6.4
Interrupt Response Times ................................................................................. 132
6.6.5
DTC and DMAC Activation by Interrupt ......................................................... 133
6.7
CPU Priority Control Function Over DTC and DMAC.................................................... 136
6.8
Usage Notes ...................................................................................................................... 139
6.8.1
Conflict between Interrupt Generation and Disabling ...................................... 139
6.8.2
Instructions that Disable Interrupts ................................................................... 140
6.8.3
Times when Interrupts are Disabled ................................................................. 140
6.8.4
Interrupts during Execution of EEPMOV Instruction ...................................... 140
6.8.5
Interrupts during Execution of MOVMD and MOVSD Instructions................ 140
6.8.6
Interrupts of Peripheral Modules ...................................................................... 141
Section 7 User Break Controller (UBC).............................................................. 143
7.1
Features............................................................................................................................. 143
7.2
Block Diagram.................................................................................................................. 144
7.3
Register Descriptions........................................................................................................ 145
7.3.1
Break Address Register n (BARA, BARB, BARC, BARD) ............................ 146
7.3.2
Break Address Mask Register n (BAMRA, BAMRB, BAMRC, BAMRD) .... 147
7.3.3
Break Control Register n (BRCRA, BRCRB, BRCRC, BRCRD) ................... 148
7.4
Operation .......................................................................................................................... 150
7.4.1
Setting of Break Control Conditions................................................................. 150
7.4.2
PC Break........................................................................................................... 150
7.4.3
Condition Match Flag ....................................................................................... 151
7.5
Usage Notes ...................................................................................................................... 152
Section 8 Bus Controller (BSC) .......................................................................... 155
8.1
Features............................................................................................................................. 155
8.2
Register Descriptions........................................................................................................ 158
8.2.1
Bus Width Control Register (ABWCR)............................................................ 159
8.2.2
Access State Control Register (ASTCR) .......................................................... 160
8.2.3
Wait Control Registers A and B (WTCRA, WTCRB) ..................................... 161
8.2.4
Read Strobe Timing Control Register (RDNCR) ............................................. 166