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參數(shù)資料
| 型號： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊模擬到數(shù)字轉換器參考手冊 |
| 文件頁數(shù)： | 83/122頁 |
| 文件大?。?/td> | 940K |
| 代理商： | QADCRM |
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QADC
REFERENCE MANUAL
INTERRUPTS
MOTOROLA
8-3
IRL1[14:12] — Queue 1 Interrupt Level
The IRL1 field establishes the queue 1 interrupt request level. The 000 state disables
queue 1 interrupts by blocking interrupt requests. When queue 1 interrupts are to be
used, the IRL1 field must be initialized to a non-zero value. Level 001 is the lowest pri-
ority software interrupt request and level 111 is the highest priority request.
IRL2[10:8] — Queue 2 Interrupt Level
The IRL2 field establishes the queue 2 interrupt request level. The 000 state disables
queue 2 interrupts by blocking interrupt requests. When queue 2 interrupts are to be
used, the IRL2 field must be initialized to a non-zero value. Level 001 is the lowest pri-
ority interrupt request and level 111 is the highest priority request.
IVB[7:0] — Interrupt Vector Base
Initialization software inputs the upper six IVB bits in the interrupt register. During in-
terrupt arbitration, the vector provided to the CPU by the QADC is made up of the up-
per six IVB bits, plus two low-order bits provided to the QADC to identify one of four
QADC interrupt requests. The interrupt vector number is independent of the interrupt
level and the interrupt arbitration number. A $0F vector number corresponds to the un-
initialized interrupt vector. After reset, the lower byte of the interrupt register reads as
$0F. Once the IVB field is written, the two least significant bits always read as zeros.
8.5 Interrupt Priority
The CPU16 and the CPU32 use an interrupt priority scheme based on that of the
68000 family. This scheme utilizes a three-bit interrupt priority mask that is located in
the CPU16 condition code register and in the CPU32 status register. The interrupt pri-
ority mask can have eight possible values, from %000 to %111.
There are seven levels of interrupt priority, one to seven, each corresponding to a par-
ticular interrupt request signal. The CPU compares the priority of each interrupt ser-
vice request to the mask value. Interrupt request levels greater than the mask value
are accepted; interrupt request levels less than or equal to the mask value are ignored,
except for the nonmaskable level seven interrupt request, which is serviced even if the
CPU interrupt mask value is seven.
The values contained in the IRL1 and IRL2 fields in the interrupt register (QADCINT)
determine the priority of QADC interrupt service requests. A value of %000 in either
field disables the interrupts associated with that field.
NOTES:
1. Reserved
2. Bits 1 and 0 supplied by the QADC.
QADCINT —
QADC Interrupt Register
$####04
15
—
1
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IRL1
—
IRL2
IVB
IVB[1:0]
2
RESET:
0
0
0
0
0
0
0
0
0
0
1
1
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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