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參數(shù)資料
| 型號： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊模擬到數(shù)字轉(zhuǎn)換器參考手冊 |
| 文件頁數(shù)： | 102/122頁 |
| 文件大小： | 940K |
| 代理商： | QADCRM |
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MOTOROLA
B-2
REGISTER SUMMARY
QADC
REFERENCE MANUAL
FRZ — Freeze Enable
0 = Ignores the IMB IFREEZE signal
1 = Finish any current conversion, then freeze
SUPV — Supervisor/Unrestricted Data Space
0 = Only the module configuration register, test register, and interrupt register are
designated as supervisor-only data space. Access to all other locations is un-
restricted.
1 = All QADC registers and tables are designated as supervisor-only data space.
IARB[3:0] — Software Interrupt Arbitration Number
IARB determines QADC interrupt arbitration priority. The reset value is $F (highest pri-
ority), to prevent QADC interrupts from being discarded during initialization.
B.2.2 QADC Test Register
QADCTEST —
QADC Test Register
QADCTEST is used only during factory testing of the MCU.
$####02
B.2.3 QADC Interrupt Register
IRL1[14:12] — Queue 1 Interrupt Level
The IRL1 field establishes the queue 1 interrupt request level. The 000 state disables
queue 1 interrupts by blocking interrupt requests. When queue 1 interrupts are to be
used, the IRL1 field must be initialized to a non-zero value. Level 001 is the lowest pri-
ority software interrupt request and level 111 is the highest priority request.
IRL2[10:8] — Queue 2 Interrupt Level
The IRL2 field establishes the queue 2 interrupt request level. The 000 state disables
queue 2 interrupts by blocking interrupt requests. When queue 2 interrupts are to be
used, the IRL2 field must be initialized to a non-zero value. Level 001 is the lowest pri-
ority interrupt request and level 111 is the highest priority request.
IVB[7:0] — Interrupt Vector Base
Initialization software inputs the upper six IVB bits in the interrupt register. During in-
terrupt arbitration, the vector provided to the CPU by the QADC is made up of the up-
per six IVB bits, plus two low-order bits provided to the QADC to identify one of four
QADC interrupt requests. The interrupt vector number is independent of the interrupt
level and the interrupt arbitration number. A $0F vector number corresponds to the un-
initialized interrupt vector. After reset, the lower byte of the interrupt register reads as
$0F. Once the IVB field is written, the two least significant bits always read as zeros.
NOTES:
1. Reserved
2. Bits 1 and 0 supplied by the QADC.
QADCINT —
QADC Interrupt Register
$####04
15
—
1
14
13
IRL1
12
11
—
1
10
9
8
7
6
5
4
3
2
1
0
IRL2
IVB
IVB[1:0]
2
RESET:
0
0
0
0
0
0
0
0
0
0
1
1
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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